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www.latticesemi.com 1 orsox2g5_06.0 orca orso42g5 and orso82g5 0.6 - 2.7 gbps sonet backplane interface fpscs august 2005 data sheet ?2005 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. introduction lattice has extended its family of high-speed serial backplane devices with the orso42g5 and orso82g5 devices. built on the series 4 recon?urable embedded system-on-a-chip (soc) architecture, the orso42g5 and orso82g5 are high-speed transceivers with aggregate bandwidths of over 10 gbits/s and 20 gbits/s respectively. these devices are targeted toward users needing high-speed backplane interfaces for sonet and other non- sonet applications. the orso42g5 has four channels and the orso82g5 has eight channels of integrated 0.6- 2.7gbits/s serdes channels with built-in clock and data recovery (cdr), along with more than 400k usable fpga system gates. the cdr circuitry, available from lattices high-speed i/o portfolio (syshsi), has already been used in numerous applications to create sts-48/stm-16 and sts-192/stm-64 sonet/sdh interfaces. with the addition of protocol and access logic, such as framers and packet-over-sonet (pos) interfaces, design- ers can build a con?urable interface using proven backplane driver/receiver technology. designers can also use the device to drive high-speed data transfer across buses within a system that are not sonet/sdh based. the orso42g5 and orso82g5 can also be used to provide a full 10 gbits/s backplane data connection and, with the orso82g5, support both work and protection connections between a line card and switch fabric. the orso42g5 and orso82g5 support a clockless high-speed interface for interdevice communication on a board or across a backplane. the built-in clock recovery of the orso42g5 and orso82g5 allows higher system performance, easier-to-design clock domains in a multiboard system and fewer signals on the backplane. network designers will bene? from using the backplane transceiver as a network termination device. sister devices, the ort42g5 and the ort82g5, support 8b/10b encoding/decoding and link state machines for 10 gbit ethernet (xaui) and fibre channel. the orso42g5 and orso82g5 perform sonet data scrambling/descrambling, streamlined sonet framing, limited transport overhead (toh) handling, plus the programmable logic to termi- nate the network into proprietary systems. the cell processing feature in the orso42g5 and orso82g5 makes them ideal for interfacing devices with any proprietary data format across a high-speed backplane. for non-sonet applications, all sonet functionality is hidden from the user and no prior networking knowledge is required. the orso42g5 and orso82g5 are completely pin-compatible with the ort42g5 and ort82g5 devices. table 1. orca orso42g5 and orso82g5 family ?available fpga logic . device pfu rows pfu columns total pfus fpga max user i/o luts ebr blocks 2 ebr bits (k) fpga system gates (k) 1 orso42g5 36 36 1296 204 10,368 12 111 333-643 orso82g5 36 36 1296 372 10,368 12 111 333-643 1. the embedded core, embedded system bus, fpga interface and mpi are not included in the above gate counts. the system gate ranges are derived from the following: minimum system gates assumes 100% of the pfus are used for logic only (no pfu ram) with 40% ebr usage and 2 plls. maximum system gates assumes 80% of the pfus are for logic, 20% are used for pfu ram, with 80% ebr usage and 4 plls. 2. there are two 4k x 36 (144k bits each) ram blocks in the embedded core which are also accessible by the fpga logic.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 2 table of contents introduction .................................................................. 1 table of contents......................................................... 2 embedded function features...................................... 3 programmable features .............................................. 4 programmable logic system features........................ 5 description ................................................................... 6 what is an fpsc? .......................................... 6 fpsc overview............................................... 6 fpsc gate counting ...................................... 6 fpga/embedded core interface .................... 6 isplever development system..................... 7 fpsc design kit ............................................. 7 orso82g5/42g5 fpga logic overview....... 7 orca series 4 fpga logic overview ........... 7 plc logic........................................................ 8 programmable i/o........................................... 8 routing............................................................ 9 system level features ................................... 9 microprocessor interface ................................ 9 system bus ..................................................... 9 phase-locked loops ...................................... 9 embedded block ram .................................. 10 configuration................................................. 10 orso42g5 and orso82g5 overview .................... 10 embedded core overview ............................ 11 orso42g5 and orso82g5 main operating modes - overview.................. 12 embedded core functional blocks - overview................................................. 13 loopback - overview .................................... 14 fpsc configuration - overview .................... 15 orso42g5 and orso82g5 embedded core detailed description ............................................ 16 top level description - transmitter (tx) and receiver (rx) architectures ............ 16 detailed description - serdes only mode....................................................... 19 32:8 mux ...................................................... 21 sonet mode operation ? detailed description ............................... 24 sonet mode transmit path ........................ 30 sonet mode receive path ......................... 33 cell mode detailed description..................... 49 cell mode transmit path............................... 52 cell mode receive path................................ 56 cell extractor................................................. 56 receive fifo ................................................ 57 input port controllers .................................... 57 ipc receive cell mode timing core/fpga ............................................. 59 reference clock requirements .................... 67 sample initialization sequences ?orso42g5......... 69 sample initialization sequences ?orso82g5......... 70 reset conditions........................................................ 72 serdes characterization test mode (orso82g5 only)............................................... 73 embedded core block ram ...................................... 74 register maps ............................................................ 76 types of registers ........................................ 77 absolute maximum ratings ..................................... 108 recommended operating conditions ...................... 108 serdes electrical and timing characteristics ....... 108 high speed data transmitter...................... 109 high speed data receiver.......................... 110 external reference clock ........................... 112 pin descriptions ....................................................... 113 power supplies ........................................................ 118 power supply descriptions ......................... 118 recommended power supply connections.......................................... 118 recommended power supply filtering scheme................................................. 118 package information ................................................ 120 package pinouts ......................................... 120 package thermal characteristics summary............ 148 ja .............................................................. 148 jc .............................................................. 148 jc .............................................................. 148 jb .............................................................. 148 fpsc maximum junction temperature ...... 149 package thermal characteristics ............... 149 heat sink vendors for bga packages........ 149 package parasitics...................................... 149 package outline drawings.......................... 150 part number description.......................................... 151 device type options................................... 151 ordering information ................................................ 151 conventional packaging ............................. 151 lead-free packaging.................................. 152
lattice semiconductor orca orso42g5 and orso82g5 data sheet 3 embedded function features high-speed serdes programmable serial data rates of 0.6 gbits/s to 2.7 gbits/s. asynchronous operation per receive channel (separate pll per channel). transmit pre-emphasis (programmable) for improved receive data eye opening. provides a 10 gbits/s backplane interface to switch fabric using four work and, with the orso82g5, four protect 2.5 gbit/s links. also supports port cards at rates between 0.6 gbits/s and 2.7 gbits/s. allows wide range of applications for sonet network termination, as well as generic data moving for high-speed backplane data transfer. no knowledge of sonet/sdh needed in generic applications. simply supply data (75 mhz-168.75 mhz clock) and at least a single frame pulse. high-speed interface (hsi) function for clock/data recovery serial backplane data transfer without external clocks. four- or eight-channel hsi functions provide 2.7 gbits/s serial user data interface per channel for a total chip bandwidth of >10gbits/s or >20 gbits/s (full duplex). serdes has low-power cml buffers and support for 1.5v/1.8v i/os. serdes hsi automatically recovers from loss-of-clock once its reference clock returns to normal operating state. powerdown option of serdes hsi receiver and/or transmitter on a per-channel basis. ability to mix half-rate and full-rate between the channels with the same reference clock. ability to con?ure each serdes block independently with its own reference clock. sts-48 framing in sonet mode. programmable enable of sonet scrambler/descrambler, a1/a2 insertion and b1 generation and checking. insertion and checking of link assignment values to facilitate interconnection and debugging of backplanes. optional ais-l insertion during loss-of-frame. optional rdi-l insertion to indicate remote far-end defects for maintenance capabilities. spe signal marks payload bytes in sonet mode. frame alignment across multiple orso42g5 and orso82g5 devices for work/protect switching at sts- 768/stm-256 and above rates. supports transparent mode where transport overhead (toh) bytes are user-generated in the fpga. supports two modes of in-band management and con?uration with toh byte extraction/insertion by the embedded core. a1/a2 and b1 insertion can be independently enabled. auto_soh where the embedded core inserts the a1/a2 framing bytes, performs the b1 calculation and inserts the b1 byte. all other bytes are passed through unchanged from the fpga logic as in transparent mode. auto_toh where all of the overhead bytes are set by the embedded core. most of the bytes are set to zero. at the receive side, all of the toh bytes except those set to a non-zero value can be ignored. optional a1/a2 corruption, b1 byte corruption, and k2 byte corruption for system debug purposes. built-in boundary scan ( ieee 1149.1 and 1149.2 jtag), including the serdes interface. fifos align incoming data across all eight channels (orso82g5 only), groups of four channels, or groups of two channels. optional ability to bypass alignment fifos for asynchronous operation between channels is also provided. (each channel includes its own recovered clock and frame pulse).
lattice semiconductor orca orso42g5 and orso82g5 data sheet 4 optional cell processing blocks included. cell processing includes cell creation, extraction, idle cell insertion and deletion asynchronous from line rates. four cell sizes supported: 77 bytes per cell (75 bytes of data payload) 81 bytes per cell (79 bytes of data payload) 85 bytes per cell (83 bytes of data payload) 93 bytes per cell (91 bytes of data payload) automatic cell striping across either pairs of serdes links or, for the orso82g5, all eight serdes links. addition of two 4k x 36 dual-port rams accessible by the programmable logic. programmable features high-performance programmable logic: 0.16 ? 7-level metal technology. internal performance of >250 mhz. over 400k usable system gates. meets multiple i/o interface standards. 1.5v operation (30% less power than 1.8v operation) translates to greater performance. traditional i/o selections: lvttl (3.3v) and lvcmos (2.5v, and 1.8v) i/os. per pin-selectable i/o clamping diodes provide 3.3v pci compliance. individually programmable drive capability: 24 ma sink/12 ma source, 12 ma sink/6 ma source, or 6 ma sink/3 ma source. two slew rates supported (fast and slew-limited). fast-capture input latch and input flip-flop (ff)/latch for reduced input setup time and zero hold time. fast open-drain drive capability. capability to register 3-state enable signal. off-chip clock drive capability. two-input function generator in output path. new programmable high-speed i/o: single-ended: gtl, gtl+, pecl, sstl3/2 (class i and ii), hstl (class i, iii, iv), zbt, and ddr. double-ended: lvds, bused-lvds, and lvpecl. programmable (on/off), internal parallel termination (100 ) is also supported for these i/os. new capability to (de)multiplex i/o signals: new ddr on both input and output. new 2x and 4x downlink and uplink capability per i/o. enhanced twin-block programmable function unit (pfu): eight 16-bit look-up tables (luts) per pfu. nine user registers per pfu, one following each lut, and organized to allow two nibbles to act indepen- dently, plus one extra for arithmetic operations. new register control in each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects. new lut structure allows ?xible combinations of lut4, lut5, new lut6, 4 1 mux, new 8 1 mux, and ripple mode arithmetic functions in the same pfu. 32 x 4 ram per pfu, con?urable as single-port or dual-port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the supplemental logic and interconnect cell (slic) decoders as bank drivers. soft-wired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu through fast internal routing which reduces routing congestion and improves speed. flexible fast access to pfu inputs from routing. fast-carry logic and routing to all four adjacent pfus for nibble-wide, byte-wide, or longer arithmetic func- tions, with the option to register the pfu carry-out.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 5 abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. hierarchical routing optimized for both local and global routing with dedicated routing resources. this results in faster routing times with predictable and ef?ient performance. supplemental logic and interconnect cell (slic) provides eight 3-statable buffers, up to a 10-bit decoder, and pa l -like and-or-invert (aoi) in each programmable logic cell. new 200 mhz embedded block-port ram blocks, 2 read ports, 2 write ports, and 2 sets of byte lane enables. each embedded ram block can be con?ured as: 1?12 x 18 (block-port, two read/two write) with optional built in arbitration. 1?56 x 36 (dual-port, one read/one write). 1?k x 9 (dual-port, one read/one write). 2?12 x 9 (dual-port, one read/one write for each). 2 rams with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). supports joining of ram blocks. two 16 x 8-bit content addressable memory (cam) support. fifo 512 x 18, 256 x 36, 1kx 9, or dual 512 x 9. constant multiply (8 x 16 or 16 x 8). dual variable multiply (8 x 8). embedded 32-bit internal system bus plus 4-bit parity interconnects fpga logic, microprocessor interface (mpi), embedded ram blocks, and embedded standard cell blocks with 100 mhz bus performance. included are built- in system registers that act as the control and status center for the device. built-in testability: full boundary scan ( ieee 1149.1 and draft 1149.2 jtag). programming and readback through boundary scan port compliant to ieee draft 1532:d1.7. ts_all testability function to 3-state all i/o pins. new temperature-sensing diode. improved built-in clock management with programmable phase-locked loops (pplls) provide optimum clock modi?ation and conditioning for phase, frequency, and duty cycle from 15 mhz up to 420 mhz. multiplication of the input frequency up to 64x and division of the input frequency down to 1/64x possible. new cycle stealing capability allows a typical 15% to 40% internal speed improvement after ?al place and route. this feature also enables compliance with many setup/hold and clock to out i/o speci?ations and may provide reduced ground bounce for output buses by allowing ?xible delays of switching output buffers. pci local bus compliant for fpga i/os. programmable logic system features improved powerpc ? 860 and powerpc ii high-speed synchronous microprocessor interface can be used for con?uration, readback, device control, and device status, as well as for a general-purpose interface to the fpga logic, rams, and embedded standard cell blocks. glueless interface to synchronous powerpc processors with user-con?urable address space provided. new embedded system bus facilitates communication among the microprocessor interface, con?uration logic, embedded block ram, fpga logic, and embedded standard cell blocks. variable size bused readback of con?uration data with the built-in microprocessor interface and system bus. internal, 3-state, and bidirectional buses with simple control provided by the slic. new clock routing structures for global and local clocking signi?antly increases speed and reduces skew. new local clock routing structures allow creation of localized clock trees. two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved
lattice semiconductor orca orso42g5 and orso82g5 data sheet 6 setup/hold and clock to out performance. new double-data rate (ddr) and zero-bus turn-around (zbt) memory interfaces support the latest high-speed memory interfaces. new 2x/4x uplink and downlink i/o capabilities interface high-speed external i/os to reduced speed internal logic. isplever development system software. supported by industry-standard cae tools for design entry, synthe- sis, simulation, and timing analysis. meets universal test and operations phy interface for atm (utopia) levels 1, 2, and 3; as well as pos-phy3. description what is an fpsc? fpscs, or field-programmable system chips, are devices that combine ?ld-programmable logic with asic or mask-programmed logic on a single device. fpscs provide the time to market and the ?xibility of fpgas, the design effort savings of using soft intellectual property (ip) cores, and the speed, design density, and economy of asics. fpsc overview lattices series 4 fpscs are created from series 4 orca fpgas. to create a series 4 fpsc, several columns of programmable logic cells (see fpga logic overview section for fpga logic details) are added to an embedded logic core. other than replacing some fpga gates with asic gates, at greater than 10:1 ef?iency, none of the fpga functionality is changed?ll of the series 4 fpga capability is retained: embedded block rams, mpi, pcms, boundary scan, etc. the columns of programmable logic are replaced at the right of the device, allowing pins from the replaced columns to be used as i/o pins for the embedded core. the remainder of the device pins retain their fpga functionality. fpsc gate counting the total gate count for an fpsc is the sum of its embedded core (standard-cell/asic gates) and its fpga gates. because fpga gates are generally expressed as a usable range with a nominal value, the total fpsc gate count is sometimes expressed in the same manner. standard-cell asic gates are, however, 10 to 25 times more silicon- area ef?ient than fpga gates. therefore, an fpsc with an embedded function is gate equivalent to an fpga with a much larger gate count. fpga/embedded core interface the interface between the fpga logic and the embedded core has been enhanced to allow a greater number of interface signals than on previous fpsc architectures. compared to bringing embedded core signals off-chip, this on-chip interface is much faster and requires less power. all of the delays for the interface are precharacterized and accounted for in the isplever development system. orca series 4 based fpscs expand this interface by providing a link between the embedded block and the multi- master 32-bit system bus in the fpga logic. this system bus allows the core easy access to many of the fpga logic functions including the embedded block rams and the microprocessor interface. clock spines also can pass across the fpga/embedded core boundary. this allows for fast, low-skew clocking between the fpga and the embedded core. many of the special signals from the fpga, such as done and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the fpga as a system. for even greater system ?xibility, fpga con?uration rams are available for use by the embedded core. this supports user-programmable options in the embedded core, in turn allowing for greater ?xibility. multiple embed- ded core con?urations may be designed into a single device with user-programmable control over which con?u- rations are implemented, as well as the capability to change core functionality simply by recon?uring the device.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 7 isplever development system the isplever development system is used to process a design from a netlist to a con?ured fpga. this system is used to map a design onto the orca architecture, and then place and route it using isplever development system timing-driven tools. the development system also includes interfaces to, and libraries for, other popular cae tools for design entry, synthesis, simulation, and timing analysis. fpsc design kit development is facilitated by an fpsc design kit which, together with isplever and third-party synthesis and sim- ulation engines, provides all software and documentation required to design and verify an fpsc implementation. included in the kit are the fpsc con?uration manager and/or complied verilog simulation model, hspice and/or ibis models for i/o buffers, and complete online documentation. the kit's software couples with isplever, provid- ing a seamless fpsc design environment. orso82g5/42g5 fpga logic overview the following sections provide a brief overview of the main architectural features of the orso82g5/42g5 fpga logic. for more detailed information, refer to the orca series 4 fpga data sheet which can be found on the lat- tice web site at www .latticesemi.com . the orca series 4 fpga data sheet provides detailed information required for designing with the orso82g5/42g5 device. topics covered in the orca series 4 data sheet include: fpga logic architecture fpga routing resources fpga clock routing resources fpga programmable input/output cells (pics) fpga embedded block ram (ebr) microprocessor interface (mpi) phase-locked loops (plls) electrical characteristics fpga timing characteristics power-up con?uration orca series 4 fpga logic overview the orca series 4 architecture is a new generation of sram-based programmable devices from lattice. it includes enhancements and innovations geared toward todays high-speed systems on a single chip. designed with networking applications in mind, the series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 4 devices contain many new patented enhance- ments and are offered in a variety of packages and speed grades. the hierarchical architecture of the logic, clocks, routing, ram, and system-level blocks create a seamless merge of fpga and asic designs. modular hardware and software technologies enable system-on-chip integration with true plug-and-play design implementation. the architecture consists of four basic elements: programmable logic cells (plcs), programmable i/o cells (pios), embedded block rams (ebrs), and system-level features. these elements are interconnected with a rich routing fabric of both global and local wires. an array of plcs are surrounded by common interface blocks which provide an abundant interface to the adjacent plcs or system blocks. routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. each plc contains a pfu, slic, local routing resources, and con?uration ram. most of the fpga logic is performed in the pfu, but decoders, pa l -like functions, and 3-state buffering can be performed in the slic. the pios provide
lattice semiconductor orca orso42g5 and orso82g5 data sheet 8 device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplex- ing, uplink and downlink functions, and other functions on two output signals. large blocks of 512 x 18 block-port ram complement the existing distributed pfu memory. the ram blocks can be used to implement ram, rom, fifo, multiplier, and cam. some of the other system-level functions include the mpi, plls, and the embedded system bus (esb). plc logic each pfu within a plc contains eight 4-input (16-bit) luts, eight latches/ffs, and one additional flip-flop that may be used independently or with arithmetic functions. the pfu is organized in a twin-block fashion; two sets of four luts and ffs that can be controlled independently. each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects. luts may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be con?ured as a synchronous 32 x 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. the slic is connected from plc routing resources and from the outputs of the pfu. it contains eight 3-state, bidi- rectional buffers, and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert to perform pa l -like functions. the 3-state drivers in the slic and their direct connections from the pfu outputs make fast, true, 3-state buses possible within the fpga, reducing required routing and allowing for real- world system performance. programmable i/o the series 4 pio addresses the demand for the ?xibility to select i/os that meet system interface requirements. i/os can be programmed in the same manner as in previous orca devices, with the additional new features which allow the user the ?xibility to select new i/o types that support high-speed interfaces. each pio contains four programmable i/o pads and is interfaced through a common interface block to the fpga array. the pio is split into two pairs of i/o pads with each pair having independent clock enables, local set/reset, and global set/reset. on the input side, each pio contains a programmable latch/flip-flop which enables very fast latching of data from any pad. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data sig- nal, and register the signals without explicitly building a demultiplexer with a pfu. on the output side of each pio, an output from the plc array can be routed to each output flip-flop, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. the output ff, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. in addition, this 3- state signal can be registered or nonregistered. the series 4 i/o logic has been enhanced to include modes for speed uplink and downlink capabilities. these modes are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing data rates. this new logic block also supports high-speed ddr mode requirements where data are clocked into and out of the i/o buffers on both edges of the clock. the new programmable i/o cell allows designers to select i/os which meet many new communication standards permitting the device to hook up directly without any external interface translation. they support traditional fpga standards as well as high-speed, single-ended, and differential-pair signaling. based on a programmable, bank-ori- ented i/o ring architecture, designs can be implemented using 3.3v, 2.5v, 1.8v, and 1.5v referenced output levels.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 9 routing the abundant routing resources of the series 4 architecture are organized to route signals individually or as buses with related control signals. both local and global signals utilize high-speed buffered and nonbuffered routes. one plc segmented (x1), six plc segmented (x6), and bused half chip (xhl) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated i/o pads, plls, plc logic or the embedded core. secondary and edge-clock routing is available for fast regional clock or control signal routing for both internal regions and on device edges. secondary clock routing can also be sourced from any i/o pin, plls, plc logic or the embedded core. the improved routing resources offer great ?xibility in moving signals to and from the logic core. this ?xibility translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to speci? pins. system level features the series 4 also provides system-level functionality by means of its microprocessor interface, embedded system bus, block-port embedded block rams, universal programmable phase-locked loops, and the addition of highly tuned networking speci? phase-locked loops. these functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in todays high-speed networking systems. microprocessor interface the mpi provides a glueless interface between the fpga and powerpc microprocessors. programmable in 8-, 16-, and 32-bit interfaces with optional parity to the motorola powerpc 860 bus, it can be used for con?uration and readback, as well as for fpga control and monitoring of fpga status. all mpi transactions utilize the series 4 embedded system bus at 66 mhz performance. the microprocessor interface (mpi) provides a system-level interface, using the system bus, to the fpga user- de?ed logic following con?uration, including access to the embedded block ram and general logic. the mpi supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data fifos. transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-beat (16 x 1 bytes). system bus an on-chip, multimaster, 32-bit system bus with 4-bit parity facilitates communication among the mpi, con?uration logic, fpga control, and status registers, embedded block rams, as well as user logic. the embedded system bus offers arbiter, decoder, master, and slave elements. master and slave elements are also available for the user- logic and a slave interface is used for control and status of the embedded backplane transceiver portion of the orso42g5 and orso82g5. the system bus control registers can provide control to the fpga such as signaling for reprogramming, reset func- tions, and pll programming. status registers monitor init, done, and system bus errors. an interrupt controller is integrated to provide up to eight possible interrupt resources. bus clock generation can be sourced from the micro- processor interface clock, con?uration clock (for slave con?uration modes), internal oscillator, user clock from routing, or from the port clock (for jtag con?uration modes). phase-locked loops up to eight plls are provided on each series 4 device, with four user plls generally provided for fpscs, includ- ing the orso42g5 and orso82g5. in the fpscs, these plls can only be driven by the fpga resources. pro- grammable plls can be used to manipulate the frequency, phase, and duty cycle of a clock signal. each ppll is capable of manipulating and conditioning clock outputs from 15 mhz to 420 mhz. frequencies can be adjusted from 1/8x to 8x, the input clock frequency. each programmable pll provides two outputs that have different multi- plication factors but can have the same phase relationships. duty cycles and phase delays can be adjusted in
lattice semiconductor orca orso42g5 and orso82g5 data sheet 10 12.5% of the clock period increments. an automatic input buffer delay compensation mode is available for phase delay. each ppll provides two outputs that can have programmable (12.5% steps) phase differences. embedded block ram new 512 x 18 block-port ram blocks are embedded in the fpga core to signi?antly increase the amount of mem- ory and complement the distributed pfu memories. the ebrs include two write ports, two read ports, and two byte lane enables which provide four-port operation. optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus. additional logic has been incorporated to allow signi?ant ?xibility for fifo, constant multiply, and two-variable multiply functions. the user can con?ure fifo blocks with ?xible depths of 512k, 256k, and 1k including asyn- chronous and synchronous modes and programmable status and error ?gs. multiplier capabilities allow a multiply of an 8-bit number with a 16-bit ?ed coef?ient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16- bit output). on-the-? coef?ient modi?ations are available through the second read/write port. two 16 x 8-bit cams per embedded block can be implemented in single match, multiple match, and clear modes. the ebrs can also be preloaded at device con?uration time. con?uration the fpgas functionality is determined by internal con?uration ram. the fpgas internal initialization/con?ura- tion circuitry loads the con?uration data at powerup or under system control. the con?uration data can reside externally in an eeprom or any other storage media. serial eeproms provide a simple, low pin-count method for con?uring fpgas. the ram is loaded by using one of several con?uration modes. supporting the traditional master/slave serial, master/slave parallel, and asynchronous peripheral modes, series 4 also utilizes its microprocessor interface and embedded system bus to perform both programming and readback. daisy chaining of multiple devices and partial recon?uration are also permitted. other con?uration options include the initialization of the embedded-block ram memories and fpsc memory as well as system bus options and bit stream error checking. programming and readback through the jtag (ieee 1149.2 ) port is also available meeting in-system programming (isp) standards ( ieee 1532 draft). orso42g5 and orso82g5 overview the orso42g5 and orso82g5 fpscs provide high-speed backplane transceivers combined with fpga logic. the orso42g5 and orso82g5 devices are based on the 1.5v or4e04 orca fpga and have a 36 x 36 array of programmable logic cells (plcs). the embedded core, which contains the backplane transceivers, is attached to the right side of the device and is integrated directly into the fpga array. a top level diagram of the basic chip con?uration is shown in figure 1.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 11 figure 1. orso42g5 and orso82g5 basic chip con?uration the orso42g5 and orso82g5 support aggregate bandwidths over 10gbits/s and are targeted towards users needing high-speed backplane interfaces for sonet and other non-sonet proprietary backplanes. for non- sonet applications, all sonet functionality is hidden from the user and no prior networking knowledge is required. built using series 4 recon?urable system-on-a-chip (soc) architecture, the orso42g5 and orso82g5 contain the fpga base array and an embedded core supporting eight serial data channels, with clock and data recovery functions, and provides sonet framing, scrambling/descrambling and cell processing on a single monolithic chip to enable high-speed asynchronous serial data transfer between system devices. devices can be on the same pc- board, on separate boards connected across a backplane or connected by cables. the orso42g5 and orso82g5 are completely pin-compatible with the ort42g5 and ort82g5 devices. the orso42g5 and orso82g5 are considered pseudo-sonet devices because they do not support full over- head processing, pointer processing or meet all sonet jitter/timing requirements. the orso42g5 and orso82g5 are designed primarily for use as sonet backplane devices and not for network termination. although they format and process data as sonet frames, they cannot terminate data directly on a sonet ring without additional functionality being implemented in the fpga logic because the embedded core is not fully sonet compliant on a stand-alone basis. the orso42g5 and orso82g5 embedded cores support the following: section/line overhead: a1/a2 (framing bytes), b1 (bip-8), k2 (aps) alarms: oof (out of frame), b1 error, rdi two modes of automatic transport overhead (toh) generation and insertion ais-l insertion spe signal generation which support +/- stuff events (but no pointer processing) embedded core overview the functions in the embedded core portion of the orso42g5 and orso82g5 devices include: eight channel 2.7 gbits/s serializer/deserializer functions with clock and data recovery (cdr). eight-bit interface to the series 4 system bus for control and status information exchange. embedded serial i/o core (4 or 8 serial channels) orca 4e04-based programmable logic fpga i/o
lattice semiconductor orca orso42g5 and orso82g5 data sheet 12 support for oc-48 and oc-192 (in block oc-48) formats. sonet framing, scrambling and sonet mode channel alignment. performance monitoring functions such as bit interleaved parity (bip-8) generation and checking and out-of- frame (oof) and remote defect indication (rdi-l) detection. cell mode cell creation and extraction, idle cell insertion/deletion, destriping and striping functions. additionally, there are two independent memory blocks in the core. each embedded ram block has a capacity of 4k words by 36 bits. the orso42g5 and orso82g5 embedded cores contain, respectively, four-channel and eight-channel clock and data recovery macrocells and logical blocks performing functions such as sonet framing, scrambling/descram- bling and cell processing. the channels each operate from 0.6 to 2.7 gbits/s with per channel cdr functionality. the cdr interface enables high-speed asynchronous serial data transfer between system devices. devices can be on the same pc-board, on separate boards connected across a backplane, or connected by cables. figure 2 shows a top level block diagram of the backplane driver logic in the embedded core (embedded ram not shown). figure 2. top level block diagram orso42g5 and orso82g5 embedded cores orso42g5 and orso82g5 main operating modes - overview the orso42g5 and orso82g5 support four and eight 0.6 to 2.7 gbits/s serial data channels respectively, which can operate independently or can be combined together (aligned) to achieve higher bit rates. the mode of opera- tion of the core is de?ed by a set of control registers, which can be written through the system bus interface. the status of the core is stored in a set of status registers, which can be read through the system bus interface. the serial data channels support oc-48 rates on each channel. the standard oc-48 rate, 2.488 gbits, is used as the nominal data rate for the technical discussions that follow. oc-192 is also supported but is transmitted and received in block oc-48 links. the scrambled data stream conforms to the gr-255 speci?d polynomial sequence of 1+x 6 +x 7 . there are three main operating modes in the orso42g5 and orso82g5 as described below: serdes only (bypass) mode sonet mode cell mode two-link sub-mode eight-link sub-mode (orso82g5 only) transmit (tx) path receive (rx) path cell processing configurable as four or eight data channels organized in two blocks user configurable i/o psuedo- sonet processing orca 4e04 fpga logic mux/demux and serdes
lattice semiconductor orca orso42g5 and orso82g5 data sheet 13 there are sub-modes that can be derived by enabling or disabling certain functions through programmable register bits. also, in cell mode, either the two-link alignment mode, for up to four alignment groups, or the eight-link align- ment mode, where all eight links are combined into a single group, may be selected. data are processed in the transmit direction (fpga to backplane) as follows: in the serdes only mode , there is the option to bypass all of the sonet and cell functions and pass raw 32-bit data from the fpga into the 32:8 mux block. in this mode, the user is responsible for providing an adequate ones transition density in the transmitted stream for clock and data recovery at the receive end of the link. in the sonet mode , a sonet frame is constructed around the input data and overhead bytes are inserted where appropriate. the 32-bits of data per channel are scrambled before being converted to 8-bits by the 32:8 mux block and serialized by the serdes. in the cell mode , 160 bits of data from the fpga is sent to the output port controller-8 block (for the orso82g5 only, the block is also referred to as opc8 since it services eight links) or 40 bits of data to an out- put port controller-2 block (referred to as the opc2) which perform cell striping across the different serdes links. the cells are then transferred to the sonet clock domain of 77.76 mhz through a transmit fifo. a sonet frame is constructed around the cell payload and overhead bytes inserted where appropriate before being sent to the mux block. the data are then converted to 8 bits by the 32:8 mux block before being serialized by the serdes. data are processed in the receive direction (backplane to fpga) as follows: in the serdes only mode , there is the option to bypass all of the sonet and cell functions and pass raw 32-bit data from the 8:32 demux block into the fpga interface. in the sonet mode , the descrambled data are sent to an alignment fifo that performs lane-to-lane deskew and aligns data within an alignment group to a single clock domain and frame pulse. the spe indicator is pro- vided to the fpga along with 32 bits of aligned data.there is an option to bypass the alignment fifos and pass data directly from the descrambler to the fpga. this mode is programmable and can be controlled per channel. in the cell mode , the sonet framed data are descrambled and passed into a cell extractor which extracts cells from the payload portion of the sonet frame. the cells are passed through a fifo which performs lane-to-lane deskew and a clock domain transfer from the sonet clock domain to the cell processing domain. the cells are passed into the input port controller block (referred to as ipc8 or ipc2 depending on whether eight or two links are serviced) which performs cell destriping before sending them to the fpga interface. this cell processing fea- ture makes the orso42g5 and orso82g5 ideal for interfacing devices with proprietary data formats across a backplane. embedded core functional blocks - overview each channel contains transmit path and receive path logic as shown in figure 2. data are processed on a channel by channel basis in the serdes only and sonet modes. channel by channel processing is also performed in the cell mode by the input port controller (ipc) and output port controller (opc) blocks. support for loopback is also provided but is not shown in figure 2. the following sections will give an overview of the pseudo sonet protocol supported by the orso42g5 and orso82g5 and a top level overview of the macrocells, which provide the ser- des only, sonet and cell mode functionality. serializer and deserializer (serdes) each serdes block is a block transceiver containing two or four channels for serial data transmission, with a per- channel selectable data rate of 0.6-2.7 gbits/s. each serdes block features high-speed cml interfaces and is designed to operate in sonet backplane applications. the transceiver is controlled and con?ured via an 8-bit slave interface on the system bus. each channel has dedicated registers that are readable and writable. the device also contains global registers for control of common circuitry and functions. there are two serdes blocks, a and b, in the embedded portion of the device. each block supports full duplex serial links in the orso82g5 (slice a contains channels aa, ab, ac, and ad while slice b contains channels ba, bb, bc, and bd). a similar naming
lattice semiconductor orca orso42g5 and orso82g5 data sheet 14 convention is used for the orso42g5. slice a contains channels ac and ad while slice b contains channels ac and ad. each serdes block contains its own dedicated plls for transmit and receive clock generation. the user provides a reference clock of the appropriate frequency (one per serdes block). the receiver plls extract the clock from the serial input data and retime the data with the recovered clock. clock divider circuitry also provides reference clocks for the fpga logic. 8:32 mux and 32:8 demux the purpose of the mux/demux block is to provide a wide, low-speed interface at the fpga portion of the orso42g5 and orso82g5 for each channel or data lane. the interface to the serdes macro runs at 1/8th the bit rate of the data lane. the mux/demux converts the data rate and bit-width so the fpga core can run at 1/4th this frequency (i.e., 1/32nd the serdes rate). this gives a range of 18.75 mhz-84.38 mhz for the data crossing the fpga/embedded core boundary on serdes only and sonet modes. sonet transmit overhead (toh) processing, framer and scrambler/descrambler (sonet and cell modes) in the transmit direction, the toh block is responsible for processing the 144 (48 x 3) toh bytes at the beginning of each row of the transport frame. the toh bytes may be transmitted transparently from the fpga logic or may be inserted by the toh block (auto_soh and auto_toh modes). the toh block can performs a1/a2 corruption by inverting the a1/a2 bytes under software control. the block can also force b1 errors by inverting the b1 byte or inject a fault indication by forcing the k2 byte to ?0000110? in the receive direction, the errors will be detected and alarms set. in sonet mode, all toh bytes can optionally be sent transparently from the fpga. for each of the receive channels, the framer logic outputs four bytes (32-bits) of received data that are frame- aligned and a frame pulse that is one clock-wide. the framer is responsible also for detecting the in-frame and out- of-frame status of the incoming data and sends out alarms (interrupts) on detecting an out-of-frame (oof) state. in the transmit direction, the scrambler logic scrambles the outgoing data using the standard sonet polynomial 1 + x 6 + x 7 . in the receive direction, the descrambler logic descrambles the incoming data using the same polynomial. multichannel alignment fifo and spe generation (for sonet mode) in sonet mode, the incoming data on the channels can be independent of one another or can be synchronized in several ways. two channels within a serdes block can be aligned together. alternately, four channels can be aligned to form a communication channel with a bandwidth of 10 gbits/s. finally, in the orso82g5, the alignment can be extended across all of the serdes to align all eight channels. individual channels within an alignment group can be disabled (i.e., power down) without disrupting other channels. a disabled channel can also be aligned to its group without a disruption to the remaining channels. this holds true only if the disabled channel had been previously enabled during alignments. cell extraction, striping and destriping (for cell mode) in the cell mode, cells are distributed across two-links or, in the orso82g5, across eight-links. in the tx direction, cell data from the fpga are ?triped across links within a link group. in the receive direction cell processing blocks extract cells from the link groups and send them to the fpga. this function is referred to as ?estriping? loopback - overview there are two types of loopback that can be utilized inside the embedded core of the orso42g5 and orso82g5, near end loopback and far end (line side) loopback. both of these loopbacks are controlled by control registers inside the orso42g5 and orso82g5 core, which are accessible from the system bus and the micro- processor interface (mpi).
lattice semiconductor orca orso42g5 and orso82g5 data sheet 15 dual port rams there are two independent memory blocks in the core. each memory block has a capacity of 4k words by 36 bits. it has one read port, one write port, and four byte-write-enable (active-low) signals. the read data from the memory block is registered so that it works as a pipelined synchronous memory block. these memory blocks are com- pletely independent of the backplane driver blocks. they are only accessible from the fpga logic and are not con- nected to the system bus. fpsc con?uration - overview con?uration of the orso42g5 and orso82g5 occurs in two stages: fpga bit stream con?uration and embedded core setup. prior to becoming operational, the fpga goes through a sequence of states, including power-up, initialization, con- ?uration, start-up, and operation. the fpga logic is con?ured by standard fpga bit stream con?uration means as discussed in the series 4 fpga data sheet. the options for the embedded core are set via registers that are accessed through the fpga system bus. the sys- tem bus can be driven by an external ppc compliant microprocessor via the mpi block or via a user master inter- face in fpga logic. a simple ip block, that drives the system by using the user interface and uses very little fpga logic, is available in the mpi/system bus application note (tn1017). this ip block sets up the embedded core via a state machine and allows the orso42g5 and orso82g5 to work in an independent system without an external microprocessor interface.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 16 orso42g5 and orso82g5 embedded core detailed description the orso42g5 and orso82g5 have four and eight channels respectively, with a high-speed serdes macro that performs clock data recovery, serializing and deserializing functions. there is also additional logic for sonet mode and cell mode data synchronization formatting and scrambling/descrambling. for all modes, the data paths can be characterized as the transmit path (fpga to backplane) and receive path (backplane to fpga); however the interface signal assignments between the fpga logic and the core differ depending on the operating mode selected. the three main operating modes in the orso42g5 and orso82g5 are: serdes only mode sonet mode cell mode two-link sub-mode eight-link sub-mode (orso82g5 only) the sonet and cell modes each support sub-modes that can be selected by enabling or disabling certain func- tions through programmable register bits. following the basic tx and rx architecture descriptions, the data format- ting and logical implementations supporting each of the operational modes are described. top level description - transmitter (tx) and receiver (rx) architectures the next sections give a top level description of the transmitter and receive architectures. the high-speed transmit and receive serial data can operate at 0.6-2.7 gbits/s depending on the state of the control bits from the system bus and the provided reference clock. for all of the architecture and clock distribution descriptions, however, the standard sonet sts-48 rate of 2,488.32 mbits/s (i.e., refclk_[p:n] = 155.52 mhz for the full rate modes) is assumed. transmitter architecture the transmitter section accepts parallel data for transmission from the fpga logic, formats it for transmission and serializes the data. it also accepts the low-speed reference clock at the refclk input and uses this clock to syn- thesize the internal high-speed serial bit clock. the serialized transmitted data are available at the differential cml output pins to drive either an optical transmitters, coaxial media or a circuit board backplane. the top level transmit architecture is shown in figure 3. the main logical blocks in the transmit path are: output port controllers (opcs) which contain the cell processing logic. sonet processing logic. transmit serdes and 32:8 mux. depending on the mode of operation, the fpga to backplane data path may include or bypass the various logical blocks.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 17 figure 3. top level overview, tx path logic, single channel receiver architecture the receiver section receives high-speed serial data at the external differential cml input pins. these data are fed to the clock recovery section which generates a recovered clock and retimes the data. therefore the receive clocks are asynchronous between channels. the data are then optionally framed, reformatted, aligned and passed to the fpga logic in various parallel data formats. the top level receiver architecture is shown in figure 4. the main logical blocks in the receive path are: receive serdes and 8:32 demux. sonet processing logic. input port controllers (ipcs) which contain the cell processing logic. depending on the mode of operation, the fpga to backplane data path may include or bypass the various logical blocks. fpga logic embedded core sonet scrambler toh block tx fifo 32:8 mux opc2/ opc8 payload block cell processing sonet processing 600 mb/s - 2.7 gb/s serdes 8 ldin xck311 1:8 demux legend: tck39x tck78x tck156x tsysclkx[a:d] x = a for block a, b for block b sysclk 156 8 (*orso82g5 only) line key: 311mhz from other links in block 77.76 mhz sysclk156x[1:2] tsysclkx[a:d] tck39x tck156x tck78x refclk (155.52mhz) nominal logic common to block 311mhz serdes-only mode sonet mode cell mode cell/sonet or all modes data from fpga or sysclk156 8* divide by 2 divide by 2 divide by 2 divide by 4 sonet scrambler
lattice semiconductor orca orso42g5 and orso82g5 data sheet 18 figure 4. top level overview, rx path logic, single channel in either the sonet or cell mode, data from the demux is then passed through a framer which word aligns and frames the data. data are then processed based on cell mode or sonet mode selection. in the sonet mode, the descrambled data are sent to an alignment fifo that performs lane-to-lane deskew and optionally aligns data within a multi-channel alignment group. in addition, supervisory features such as bip error check, oof check, rdi monitoring and ais-l insertion during oof are also implemented. all the supervisory fea- tures are controlled through programmable register bits. in the cell mode, the framed data are then descrambled and passed into a cell extractor which extracts cells from the payload portion of the sonet frame. the cells are passed through a fifo that performs lane-to-lane deskew and a clock domain transfer from 77.76 mhz to 155.52 mhz. a key feature in cell mode is the ability to use idle cell insertion and deletion for automatic rate matching between the clock domains. the cells are then passed to the ipc2 block (or, in the orso82g5, to the ipc8 block) which perform cell destriping before sending the cells to the fpga logic across the core/fpga interface. serdes transmit and receive plls the high-speed transmit and receive serial data can operate at 0.6 to 2.7 gbits/s depending on the state of the control bits from the system bus. table 2 shows the relationship between the data rates, the reference clock, and the internal transmit tck78x clocks. legend: rck78x x = a for block a, b for block b rwckxx xx = [ac, ad, bc, bd] for orso42g5 xx = [aa...bd] for orso82g5 ipcj_dout j = [a2, b2] for orso42g5 j = [a1, a2, b1, b2, 8] for orso82g5 fp = frame pulse line key: serdes-only mode sonet mode cell mode cell/sonet or all modes 1:8 demux fpga logic data to fpga embedded core 8:32 demux channel alignment fifo sonet framer/ descrambler cell extractor, rxfifo ipc2 or ipc8 sonet processing cell processing 600mb/s -2.7gbps serdes 8 ldout rbc refclk (155.52mhz) nominal spe generator spe 32 32 fp ipcj_dout sysclk156x[1,2] 32 fp from other links in block 77.76 mhz rck78x rw ckxx rsysclkx[1,2] doutxx[31: 0] doutxx_fp logic common to block
lattice semiconductor orca orso42g5 and orso82g5 data sheet 19 table 2. transmit pll clock and data rates the receiver section receives high-speed serial data at its differential cml input port. these data are fed to the clock recovery section which generates a recovered clock and retimes the data. this means that the receive clocks are asynchronous between channels. the retimed data are deserialized and presented as a 8-bit parallel data on the output port. rwckx receive byte clocks are divide-by-4 clocks of the rbc (recovered byte clock) clock pro- vided by the serdes. this is the clock used in the internal receive functions of the embedded core. the reference clock is also used by the receive pll for operation when the input data are not toggling appropri- ately. table 3 shows the relationship between the data rates, the reference clock, and the rwckx clocks. table 3. receive pll clock and data rates the differential reference clock is distributed to all channels in a serdes block. each channel has a differential buffer to isolate the clock from the other channels. the input clock is preferably a differential signal; however, the device can operate with a single-ended input. the input reference clock directly impacts the transmit data eye, so the clock should have low jitter. in particular, jitter components in the dc-5 mhz range should be minimized. detailed description - serdes only mode the serdes only (or bypass) mode is the simplest of the three operating modes for the orso42g5 and orso82g5. in this mode, all of the sonet and cell logic block functions are bypassed and data are transferred directly between the mux and demux blocks to and from the fpga interface. this mode is utilized when the user wants to perform all data processing and uses only the serdes portion of the embedded core. for example, this mode could be utilized to replace an existing design using stand-alone serdes and fpgas. the basic data paths in the transmit and receive directions are shown in figure 5. in general, the descriptions in this section are written to describe the serdes only mode, although the ?erdes blocks are also used in sonet and cell mode operation. at the backplane interface, data are transmitted and received serially over pairs data rate reference clock tck78x rate 0.6 gbits/s 75.00 mhz 18.75 mhz half 1.0 gbits/s 125.00 mhz 31.25 mhz half 1.244 gbits/s 155.52 mhz 38.88 mhz half 1.35 gbits/s 168.75 mhz 42.19 mhz half 2.0 gbits/s 125.00 mhz 61.50 mhz full 2.488 gbits/s 155.52 mhz 77.76 mhz full 2.7 gbits/s 168.75 mhz 84.38 mhz full notes: 1. the selection of full-rate or half-rate for a given reference clock speed is set by the txhr bit in the transmit control register and can be set per channel. (for cell mode all channels of a group must have the same txhr selection.) data rate reference clock rwckx clocks rate 0.6 gbits/s 75.00 mhz 18.75 mhz half 1.0 gbits/s 125.00 mhz 31.25 mhz half 1.244 gbits/s 155.52 mhz 38.88 mhz half 1.35 gbits/s 168.75 mhz 42.19 mhz half 2.0 gbits/s 125.00 mhz 61.50 mhz full 2.488 gbits/s 155.52 mhz 77.76 mhz full 2.7 gbits/s 168.75 mhz 84.38 mhz full note: the selection of full-rate or half-rate for a given reference clock speed is set by the rxhr bit in the receive control register and can be set per channel. (for cell mode all chan- nels of a group must have the same rxhr selection).
lattice semiconductor orca orso42g5 and orso82g5 data sheet 20 of differential 0.6 to 2.7 gbit/s links. at the fpga/embedded core interface, the data are transferred across 32-bit buses. the serdes blocks themselves are organized as two blocks. each of the data paths is identi?d with a block and channel identi?r (i.e., ac, ad, bc, bd or aa,...,bd). each channel has a 32-bit tx bus, 32-bit rx bus, a recovered clock, a transmit clock input and a transmit start sig- nal. figure 5. basic data flows - serdes only mode figure 6 shows a block diagram of a single channel of the serdes block. the transmitter section accepts either scrambled or un-scrambled data at the parallel input port. it also accepts the low-speed reference clock at the ref- clk input and uses this clock to synthesize the internal high-speed serial bit clock. the serialized data are avail- able at the differential cml output terminated in 86 to drive either an optical transmitter, coaxial media or a circuit board/backplane. figure 6. serdes functional block diagram for one channel transmit (tx) path receive (rx) path cell processing pseudo- sonet processing configurable orca 4e04 fpga logic mux/demux and serdes configurable as four or eight data channels organized in two serdes blocks user i/o tx pll serial output control hdout p/n xck311 mux ldin[7:0] hamp pe data rate txhr rx pll refclk p/n rwck ldout[7:0] parallel rbc rxhr lckrefn hdin p/n nelb felb
lattice semiconductor orca orso42g5 and orso82g5 data sheet 21 the receiver section receives high-speed serial data at its differential cml input port. these data are fed to the clock recovery section which generates a recovered clock and retimes the data. this means that the receive clocks are asynchronous between channels. the retimed data are deserialized and presented as an 8-bit parallel data on the output port. two-phase receive byte clocks are available synchronous with the parallel words. a fractional band-gap voltage generator is included on the design. an external resistor (3.32 k ?1%), connected between the pins rext and vssrext generates the bias currents within the chip. this resistor should be able to handle at least 300 ?. 32:8 mux the mux block is responsible for converting 32 bits of data at 77.76 mhz to 8 bits of data at 311.04 mhz. it will contain a small elastic store for clock domain transfer between the write clock from the fpga to the divide-by-4 clock from the serdes output clock (xck311). it is recommended to use the clocking scheme shown later in figure 27, figure 28 and figure 29 to guarantee that this elastic store will not be overrun. the 32:8 mux is also responsible for producing the divide-by-4 clock from the serdes output clock (xck311) which is 311.04 mhz at a line rate of 2.488 gbits/s. in the mux block 32-bit data synchronous to the 77.76 mhz is multiplexed to ldoutx[7:0] synchronous to the 311.04 mhz serdes output clock. parallel 32-bit data can be received directly from the fpga logic (serdes only mode) or from the payload sub-block. bit and byte alignment for the mux block is shown in figure 7. figure 7. bit and byte alignment for mux block the serialized data are available at the differential cml outputs to drive either an optical transmitter, coaxial media, or circuit board/backplane. the transmitters cml output buffer is terminated on-chip by 86 to optimize the data eye as well as to reduce the number of discrete components required. the differential output swing reaches a max- imum of 1.2 v pp in the normal amplitude mode. a half amplitude mode can be selected via con?uration register bit hamp_xx. half amplitude mode can be used to reduce power dissipation when the transmission medium has min- imal attenuation or for testing of the integrity (loss) of the physical medium. a programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maxi- mize the data eye opening at the far-end receiver. preemphasis is particularly useful when the data are transmitted over backplanes or low-quality coax cables which have a frequency-dependent amplitude loss. for example, for fr4 material at 2.5 ghz, the attenuation compared to the 1.0 ghz value is about 3 db. the attenuation is a result of skin effect loss of the pcb conductor and the dielectric loss of the pcb substrate. this attenuation causes inter- symbol interface which results in the closing of the data eye at the receiver. time w o r d 3 w o r d 2 w o r d 1 w o r d 0 32:8 mux w 0 w 1 w 2 w 3 bit and byte alignment of the 32-bit 77mhz data ldin[0:7] through the 32:8 mux block to ldin[0:7 is shown in the diagram to the left. 7 0 7 0 31 0
lattice semiconductor orca orso42g5 and orso82g5 data sheet 22 since this effect is predictable for a given type of pcb material, it is possible to compensate for this effect in two ways - transmitter preemphasis and receiver equalization. each of these techniques boosts the high frequency components of the signal but transmit preemphasis is preferred due to the ease of implementation and the better power utilization. it also gives a better signal-to-noise ratio because receiver equalization ampli?s both the signal and the noise at the receiver. applying too much preemphasis when it is not required, for example when driving a short backplane path, will also degrade the data eye opening at the receiver. in the orso42g5 and orso82g5, the degree of transmit preem- phasis can be programmed per channel with two control register bits as shown in table 4. the high-pass transfer function of the preemphasis circuit is given by the following equation, where the value of a is shown in table 4. h(z) = (1 ?az ? ) table 4. preemphasis settings serdes receive path the receiver section receives high-speed serial data at its differential cml input port. these data are fed to the clock recovery section which generates a recovered clock and retimes the data. each serdes receive channel has its own pll and this means that the receive clocks are asynchronous between channels. this also enables each receive channel to either operate in half-rate or full-rate mode.the retimed data are deserialized and pre- sented as a 8-bit parallel data on the output port. two-phase receive byte clocks (rbc0 and rbc1) are available synchronous with the parallel words. rbc0 has its rising edge aligned to the center of the receive byte. rbc1 has its falling edge aligned to the center of the receive byte. the 8-bit data (ldout) as shown in figure 8, changes on a single clock edge (rising edge of rbc0 or falling edge of rbc1). figure 8. serdes receive path timing pe1 pe0 amount of preemphasis (a) 0 0 0% (no preemphasis, default) 0 1 12.5% 1 0 12.5% 1 1 25% ..... ldout[7:0] rbc0x rbc1x q 7 r 1 r 0 s 7 p 3 p 2 p 1 p 0 ..... p 7 p 6 p 5 p 4 r 7 r 6 r 5 r 4 r 3 r 2 s 6 s 5 s 4 s 3 p hdinx ldout[7:0] 1-bit 8-bit ..... ..... latency p q r s setup hold
lattice semiconductor orca orso42g5 and orso82g5 data sheet 23 the receive pll has two modes of operation as follows: lock to reference and lock to data with retiming. the con- trol bit lckrefn_xx selects the operating mode. when setup to lock to data and no data or invalid data are present on the hdinp and hdinn pins, the receive vco will not lock to data and its frequency can drift outside of the nominal ?00 ppm range. under this condition, the receive pll will lock to refclk for a ?ed time interval and then will attempt to lock to receive data. the process of attempting to lock to data, then locking to clock will repeat until valid input data exists. the default mode is lock to reference. the recovered byte clock (rbc0) is only centered on the data when operating in the lock to data mode. in the lock to reference mode, rbc0 is not centered on the data and may not capture the correct byte value. the serdes receives msb ?st and lsb last. hence ldoutx[7] is the bit that is received ?st and ldoutx[0] is the bit that is received last. 8:32 demux the serdes provides an eight bit data bus, and a clock, rbc0, which has a rising edge which occurs in the cen- ter of the valid data region. the demux block will create one 32-bit data word from the single 8-bit bus. the demux block will also provide a 77.76 mhz clock (divide-by-4 clock of rbc0) called rwckxx to the rest of the logic blocks such as the framer, descrambler, cell extractor and fifos. figure 9. 8:32 demux block in the demux block, ldoutx[7:0] is demultiplexed to a 32-bit data bus synchronous to the derived 77.76 mhz clock generated by dividing the 311.04 mhz clock by four. the 77.76 mhz clock is used by the remaining embed- ded blocks, as well as being fed to the fpga. receive data from the demux block is unframed. parallel data can be sent directly to the fpga logic (serdes only mode) or to the framer block for processing. bit and byte align- ment for the demux block is shown in figure 10. from serdes rbc (311 mhz) 8 ldoutx[7:0] 8:32 demux 32 @ 77.76 mhz 77.76 mhz to framer block or final output mux rwckxx
lattice semiconductor orca orso42g5 and orso82g5 data sheet 24 figure 10. bit and byte alignment for demux block sonet mode operation ?detailed description the following sections describe the data processing performed in the sonet logic blocks. the basic data ?ws in the sonet mode are shown in figure 11. at a top level, the descriptions are separated into processing in the transmit path (fpga to serial link) and processing in the receive path (serial link to fpga). in general, the descrip- tions in the next sections are written to describe sonet mode operation, although some of the ?onet logic blocks are also used in cell mode operation. the various processing options are selected by setting bits in control registers and status information is written to status registers. both types of registers can be written and/or read from the system bus. memory maps and descriptions for the registers are given in table 21 through table 36. figure 11. basic data flows - sonet mode in the sonet mode, the transmit block receives 32-bit wide data from the fpga (dinxx) on each of its channels along with a frame pulse (dinxx_fp) per channel and a transmit clock (tsyclkxx). typically this will represent a sts-48 stream on each link. the data are ?st passed through a toh block which will generate all the timing pulses that are required to isolate individual overhead bytes (e.g., a1, a2, b1, d1-d3, etc.). the timing pulse gener- time w o r d 3 w o r d 2 w o r d 1 w o r d 0 8:32 demux w 0 w 1 w 2 w 3 bit and byte alignment of ldout[0:7] through the 8:32 demux block to the 32-bit 77mhz data bus 7 0 7 0 31 0 pseudo- sonet processing user i/o receive (rx) path transmit (tx) path cell processing pseudo- sonet processing configurable orca 4e04 fpga logic mux/demux and serdes configurable as four or eight data channels organized in two blocks
lattice semiconductor orca orso42g5 and orso82g5 data sheet 25 ation will be based on the system frame pulse (dinxx_fp) received from the fpga logic, hence it is recommended that, for multi-channel alignment at the receiver, the frame pulses for the channels in an alignment group be syn- chronized. the data are then scrambled before being sent to the serdes. in the receive direction, the two sonet blocks process the receiving channels which can be treated as sts-192 streams or as independent sts-48 streams.the clocks for the received data are recovered from the received serial data streams and a serial to parallel conversion is performed on the data. the frame format of the incoming data are reconstructed (optional). the data then is descrambled using the standard sonet polynomial and a b1 parity error check is performed on the data from the previously transmitted frame. in the sonet mode, the incoming serial data streams can be aligned by groups of two, four or, in the orso82g5, eight. when doing multichannel alignment of two or more data streams, the receiver can handle the data streams with frame offsets of up to 18 78mhz clock cycles due to timing skews between cards and along backplane traces or other transmission medium. for multichannel alignment capability to operate properly, it should be noted that while the skew between channels can be very large, they must operate at the exact same frequency (0 ppm fre- quency deviation), thus requiring that the transmitters sourcing the data being received be driven by the same clock source. it is highly recommended that the frame pulses, dinxx_fp, for all links in an alignment group be synchro- nized. (see table 11 and table 12 for details of the core/fpga transmit direction signal assignments.) the received data streams are processed and passed to the fpga logic as 32-bit words. in sonet mode, doutxx[31:0] carries the 32 bit data from the alignment fifo of the respective channel and an accompanying frame pulse, doutxx_fp. other core/fpga carries miscellaneous information such as oof, biperr, and spe indicator. (see table 13 and 14 for details of the core/fpga receive direction signal assignments.) basic sonet frame format an sts-n frame can be broadly divided into the transport overhead (toh) and the synchronous payload enve- lope (spe) areas. the toh comprises of bytes that are used for framing, error detection and various other func- tions. the start of the spe can begin at any point in a sonet frame. the start of the spe is determined using the pointer bytes located in the toh. the basic sts-1 frame is shown in figure 12. higher rate sts_n signals are cre- ated by byte interleaving n sts-1 signals. some toh bytes have slightly different functions in sts-n frames than in the basic sts-1 frame. the orso42g5 and orso82g5 offer two options for processing the toh bytes, as dis- cussed in a later section. figure 12. sts-1 frame format transport overhead (toh) synchronous payload envelope (spe) 3 columns 90 columns 9 rows
lattice semiconductor orca orso42g5 and orso82g5 data sheet 26 supported data formats the orso42g5 and orso82g5 in the sonet mode support the following formats: single oc-48 on each of the channels at a bit rate of 2.488 gbits/s. oc-192 received in block oc-48 format on four channels at a combined rate of 9.952 gbits/s. the orso42g5 and orso82g5 serdes will operate at the oc-12 rate of 622 mhz. for this rate, refclk is set to 77 mhz and the serdes is used in half rate mode. however the embedded core sonet framing/process- ing logic is ?ed at the oc-48 rate and therefore can not talk directly with standard sts-12 devices. in order to interoperate with standard sts-12 devices, the user must bypass the sonet functionality in the orso embedded core (serdes-only mode) and implement all framing, toh and scrambling/descrambling functionality in fpga logic. figure 13 reveals the byte-ordering of the individual sts-48 streams. sts-192 is supported but it must be received in the block sts-48 format as shown in figure 14. each oc-48 stream is composed of byte-interleaved oc-1 data as described in gr-253 standard. note that the spe data is not touched by the core.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 27 figure 13. byte ordering of input/output interface in sts-48 mode 12 9 6 3 11 8 5 2 10 7 4 1 13 16 19 22 14 17 20 23 15 18 21 24 26 34 31 28 25 37 40 43 46 38 41 44 47 39 42 45 48 sts-48 #1 29 32 35 27 30 33 36 12 9 6 3 11 8 5 2 10 7 4 1 13 16 19 22 14 17 20 23 15 18 21 24 26 34 31 28 25 37 40 43 46 38 41 44 47 39 42 45 48 sts-48 #2 29 32 35 27 30 33 36 12 9 6 3 11 8 5 2 10 7 4 1 13 16 19 22 14 17 20 23 15 18 21 24 26 34 31 28 25 37 40 43 46 38 41 44 47 39 42 45 48 sts-48 #3 29 32 35 27 30 33 36 12 9 6 3 11 8 5 2 10 7 4 1 13 16 19 22 14 17 20 23 15 18 21 24 26 34 31 28 25 37 40 43 46 38 41 44 47 39 42 45 48 sts-48 #4 29 32 35 27 30 33 36 arrows show direction of data flow
lattice semiconductor orca orso42g5 and orso82g5 data sheet 28 figure 14. byte ordering of input/output interface in sts-192 (block sts-48) mode 12 6 3 11 8 5 2 10 7 4 1 13 19 22 14 17 20 23 15 18 21 24 26 34 31 28 25 37 43 46 38 41 44 47 39 42 45 48 sts-48 #1 60 57 54 51 59 56 53 50 58 55 52 49 61 64 67 70 62 65 68 71 63 66 69 72 84 81 78 75 83 80 77 74 82 79 76 73 85 88 91 94 86 89 92 95 87 90 93 96 sts-48 #2 108 105 102 99 107 104 101 98 106 103 100 97 109 112 115 118 110 113 116 119 111 114 117 120 132 129 126 123 131 128 125 122 130 127 124 121 133 136 139 142 134 137 140 143 135 138 141 144 sts-48 #3 156 153 150 147 152 149 146 151 145 157 160 163 166 158 161 164 167 159 162 165 168 180 177 174 171 179 176 173 170 178 175 172 169 181 184 187 190 182 185 188 191 183 186 189 192 sts-192 in sts-48 #4 block sts-48 format 29 32 35 27 30 36 148 154 155 arrows show direction of data flow 9 16 40 33
lattice semiconductor orca orso42g5 and orso82g5 data sheet 29 sonet toh byte de?itions the transport overhead bytes of the sonet frame can be used for in-band con?uration, service, and manage- ment since it is carried along the same channel as data. in the orso42g5 and orso82g5 in-band signaling can be ef?iently utilized, since the total cost of overhead is only 3.3%. the overhead bytes in an sts-1 header are shown in table 15 (the path overhead bytes are in the spe.) figure 15. sonet overhead bytes when used in true sonet applications, all or most toh bytes will be generated in the fpga logic or by an exter- nal device. two modes are provided for this application ?transparent and auto_soh. in transparent mode all bytes from the fpga logic are passed through unchanged. in auto_soh mode the embedded core inserts the a1/a2 framing bytes, performs the b1 calculation and inserts the b1 byte. a1/a2 and b1 insertion can be independently enabled. this avoids the need to do sonet scrambling in the fpga logic. all other bytes are passed through unchanged from the fpga logic as in transparent mode. when used for applications that transfer non-sonet data, an auto_toh mode is provided. in this mode, all of the overhead bytes are set by the embedded core. most of the bytes are set to zero. at the receive side, all of the toh bytes except those set to a non-zero value can be ignored in the auto_toh mode. the toh bytes have the following functions in true sonet applications. section overhead bytes: a1, a2 ?these bytes are used for framing and to mark the beginning of a sonet frame. a1 has the value 0x f6 and a2 has the value 0x28. j0 -section trace message ?this byte carries the section trace message. the message is interpreted to verify connectivity to a particular node in the network. b1 - section bit interleaved parity (bip-8) byte ?this byte carries the parity information which is used to check for transmission errors in a section. the computed parity value is transmitted in the next frame in the b1 position. it is de?ed only for the ?st sts-1 of a sts-n signal. the other bytes have a default value of 0x00. j1 b3 c2 h4 g1 f2 z4 z5 z6 a1 a2 j0 b1 e1 f1 d1 d2 d3 h1 h2 h3 b2 k1 k2 d4 d5 d6 d7 d8 d9 d10 d11 d12 s1/z1 z3 e2 j1 b3 c2 h4 g1 f2 z4 z5 z6 0 1 4 3 2 5 6 7 8 transport overhead path overhead 012 line overhead section overhead
lattice semiconductor orca orso42g5 and orso82g5 data sheet 30 e1 - section order wire byte - this byte carries local orderwire information, which provides for a 64 kbps voice channel between two section termination equipment (ste) devices. f1 - section user channel byte - this byte provides a 64 kbits/s user channel which can be used in a propri- etary fashion. d1, d2, d3 - section data communications channel (sdcc) bytes - these bytes provide a 192 kbits/s channel for transmission of information across stes. this information could be for control and con?uration, status monitoring, alarms, network administration data etc. line overhead bytes: h1, h2 - sts payload pointers (h1 and h2) - these bytes are used to locate the start of the spe in a sonet frame. these two bytes contain the offset value, in bytes, between the pointer bytes and the start of the spe. these bytes are used for all the sts-1 signals contained in an sts-n signal to indicate the individ- ual starting positions of the spes. they bytes also contain justi?ation indications, concatenation indications and path alarm indication (ais-p). h3 - pointer action byte (h3) - this byte is used during frequency justi?ations. when a negative justi?ation is performed, one extra payload byte is inserted into the sonet frame. the h3 byte is used to hold this extra byte and is hence called the pointer action byte. when justi?ation is not being performed, this byte contains a default value of 0x00. b2 - line bit-interleaved parity code (bip-8) byte - this byte carries the parity information which is used to check for transmission errors in a line. this is a even parity computed over all the bytes of the frame, except section overhead bytes, before scrambling. the computed parity value is transmitted in the next frame in the b2 position. this byte is de?ed for all the sts-1signals in an sts-n signal. k1, k2 - automatic protection switching (aps channel) bytes - these bytes carry the aps information. they are used for implementing automatic protection switching and for transmitting the line alarm indication sig- nal (ais-l) and the remote defect indication (rdi-l) signal. d4 to d12 - line data communications channel (dcc) bytes - these bytes provide a 576 kbps channel for transmission of information. s1- synchronization status - this byte carries the synchronization status of the network element. it is located in the ?st sts-1 of an sts-n. bits 5 through 8 of this byte carry the synchronization status. z1 - growth - this byte is located in the second through nth sts-1s of an sts-n and are allocated for future growth. an sts-1 signal does not contain a z1 byte. m0 - sts-1 rei-l - this byte is de?ed only for sts-1 signals and is used to convey the line remote error indication (rei-l). the rei-l is the count of the number of b2 parity errors detected by an lte and is trans- mitted to its peer lte as feedback information. bits 5 through 8 of this byte are used for this function. e2 - orderwire byte - this byte carries for line orderwire information. sonet mode transmit path the transmit block performs the following functions in sonet mode: a1 and a2 insertion and optional corruption bip-8 parity calculation, b1 byte insertion and optional corruption. (b1 byte is inverted.) performs rdi insertion (k2 byte is set to ?000 0110?. scrambling of outgoing data with optional scrambler disabling. in either sts-192 or sts-48 mode, each link operates at an sts-48 rate. tx frame processor the tx_frame_processor (tfp) block is the primary data processing block in the both sonet mode and cell mode. it organizes the cell data into a sonet frame before sending it to the serdes. the tfp is on the tsy- clkxx clock domain (77.76 mhz). in sonet mode, the 32-bit data comes from the fpga interface. (in cell mode the data comes from the cell processing block as described in the cell mode section) the tfp block contains three major sub-blocks: payload block, toh block and scrambler block. the interfaces for the tfp block are shown in figure 16.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 31 figure 16. tx frame processor (tfp) block diagram payload sub-block the payload sub block is activated by the cell mode frame pulse (cell mode) or dinxx_fp from fpga (sonet mode). a pulse on this signal indicates the start of a frame. in sonet mode, only two types of data bytes are in each frame: toh bytes spe data bytes there are n x 3 (n = 48) bytes of toh per row and there are a total of 9 rows in a sonet frame. the rest of the bytes in each row are spe data bytes in sonet mode. toh sub-block this block is responsible formatting the 144 (48 x 3) bytes of toh at the beginning of each row of the transport frame. all toh bytes may be transmitted transparently from the fpga logic using the transparent mode. alter- nately, some or all toh bytes may be inserted by the toh block (auto_soh and auto_toh mode). the toh data is transferred across the fpga/core interface as 32-bit words, hence 36 clock cycles (12 x 3) are needed to transfer a toh row. toh insertion is controlled by software register bits as shown in the register map tables. mux block ldin(7:0) xck311 payload block transport overhead block scramble logi c 32-bit pa yload scramble_disab le tx_frm_proc serdes interface fpga interface (sonet mode) 32-bit toh dat a error injection controls (control register bits) cell mode frame pulse dinxy_fp scramble_out (31:0) dinxy[31:0] data
lattice semiconductor orca orso42g5 and orso82g5 data sheet 32 table 5. inserted toh values (all 0x) in auto_soh mode the toh values inserted in auto_soh mode are shown in table 5. if a speci? value is not listed in the table, the bytes are transmitted transparently from the fpga logic as in the transparent mode. optionally k2 can be inserted by the core using the force_rdi_xx control register bits. a1/a2 and b1 insertion can be independently enabled. the toh values inserted in auto_toh mode are shown in table 6. the values are for all sts-1s in the sts-48 frame unless noted otherwise. table 6. inserted toh values (all 0x) in auto_toh mode the toh block can perform a1/a2 corruption by inverting the a1/a2 bytes and also can forces b1 errors by invert- ing the b1 byte. a rdi can be injected by forcing the k2 byte to ?0000110? in sonet mode, all toh bytes can be transparently sent from the fpga as an option. error and rdi insertion are controlled by software register bits as shown in the register map tables. scramble sub-block the scrambler scrambles the incoming 32-bit data using the standard sonet polynomial 1 + x 6 + x 7 . the scram- bler can be disabled by a software register bit. 32:8 mux the mux block is responsible for converting 32 bits of data at 77.76 mhz to 8 bits of data at 311.04 mhz. it will contain a small elastic store for clock domain transfer between the write clock from the fpga to the divide-by-4 clock from the serdes output clock (xck311). it is recommended to use the clocking scheme shown to guaran- a1 = f6 a2 = 28 j0 b1 = calculated, 1st. sts-1 b1 = 00, other sts-1s e1 f1 d1 d2 d3 h1 h2 h3 b2 k1 k2 d4 d5 d6 d7 d8 d9 d10 d11 d12 s1 m1 e2 a1 = f6 a2 = 28 j0 = sts-1 id, every 4th. sts-1 j0 = 00, other sts-1s b1 = calculated, 1st. sts-1 b1 = 00, other sts-1s e1 = 00 f1 = link number, 1st. sts-1 f1 = 00, other sts-1s d1 = 00 d2 = 00 d3 = 00 h1 = 62, 1st. sts-1 h1 = 93 other sts-1s h2 = 0a, 1st. sts-1 h2 = ff other sts-1s h3 = 00 b2 = 00 k1 = 00 k2 = 06 for rdi, k2 = 00 otherwise, 1st. sts-1 k2 = 00, other sts-1s d4 = 00 d5 = 00 d6 = 00 d7 = 00 d8 = 00 d9 = 00 d10 = 00 d11 = 00 d12 = 00 s1 = 00 m1 = 00 e2 = 00
lattice semiconductor orca orso42g5 and orso82g5 data sheet 33 tee that this elastic store will not be overrun. the 32:8 mux is also responsible for producing the divide-by-4 clock from the serdes output clock (xck311) which is 311.04 mhz at a line rate of 2.488 gbits/s. sonet mode transmit timing figure 17 shows the transmit clocks and a recommended clocking scheme. as shown, tck78[a,b] can be used to the source tsysclkxx signals. it is a requirement that tsysclkxx be frequency locked to the corresponding tck78[a,b] clock signal derived from refclk_[a:b]. figure 17. transmit clocking diagram in sonet mode when operating in sonet mode, the entire sonet frame is sent by the user. optionally the toh bytes can be overwritten by the transmit block (auto_soh or auto_toh) before sending to scrambler and serdes block. each sonet frame is 125 ? given a 155.52mhz reference clock. the frame starts with 36 clock cycles (77.76 mhz) of toh followed by 1044 clock cycles of spe, followed by 36 clock cycles of toh, 1044 cycles of spe etc. for all nine rows. figure 18. transmit sonet mode sonet mode receive path the receiver block receives a byte from the serdes blocks for each of the channels. the byte arrives at the receiver block at 311.04 mhz. this data are not frame-aligned or word aligned. the data are ?st passed through a divide-by-4 demux which produces a 32-bit word at 77.76 mhz. data from the demux is then passed through a framer which aligns and frames the data. data are processed based on cell mode or sonet mode. in the sonet mode, the descrambled data are sent to an alignment fifo that performs lane-to-lane deskew and aligns data within an alignment group to the rsyclk clock domain. both the write and read clocks to the align- xck311 ldin[7:0] 32:8 mux 32 fpga tck78[a:b] toh block tsysclk xx xx represents ac, ad, bc, bd (orso42g5) or aa, ab, ac, ad, ba, bb, bc, bd (orso82g5) 32 dinxx_fp dinxx[31:0] scrambler logic common to each block tsysclkxx dinxx[31:0] dinxx_fp ttttts s tt t tt t t s ts s ss s t ... 1 cycle 36 cycles toh 1044 cycles spe 36 cycles toh start of frame start of frame 125 s data t represents toh s represents spe xx represents ac, ad, bc, bd (orso42g5) or aa, ab, ac, ad, ba, bb, bc, bd (orso82g5). 36 cycles toh
lattice semiconductor orca orso42g5 and orso82g5 data sheet 34 ment fifo should be at exactly the same frequency (0 ppm difference), i.e., from a common clock source. later in this data sheet, figures 22, 23, 27, 28, and 29 show the recommended clocking scheme to adhere to this require- ment. in addition, supervisory features such as bip error check, oof check, rdi monitoring and ais-l insertion during oof are also implemented. all the supervisory features are controlled through programmable register bits. framer the frame and byte phase of the bits within the 32-bit word from the demux is random. for each of the sts-48 channels, the framer outputs 4 bytes (32-bits) that are frame-aligned and a frame pulse that is one clock-wide. the transition from a1 bytes to a2 bytes should happen on a 32-bit boundary. if any two consecutive bytes of the 4- byte-aligned word match the a1-a2 pattern (0xf628 in standard sonet framing), the byte-aligned word will be byte rotated to achieve frame alignment. framer state machine (fsm) the framer fsm is responsible for detecting the in-frame and out-of-frame status of the incoming data and sends out alarms (interrupts) on out-of-frame (oof). the framer is a pseudo-sonet framer in the sense that it does not support lof or sef detect-alarm signal as speci?d in the gr-253 standard. the framer has a fast frame mode where a single good framing pattern can cause the framer state machine to go the ?n_frm state and a single bad frame can cause the state machine to declare ?of (see fig. 19). the fast frame mode can be set by the software register bit, ffrm_en_xx. the fsm is a four byte framer and searches for the framing pattern based on the 32-bit words. accordingly, the framing pattern is four a1 bytes (f6,f6,f6,f6) followed by four a2 bytes (28,28,28,28). the framer fsm comes out of reset in the ?of state with the oof alarm set. the framer goes in frame if it ?ds 2 consecutive frames with the desired framing bytes and goes out of frame if it ?ds 4 consecutive frames with at least one framing bit error in each frame. frame timing is also synchronized based on the sts-48 row and column counters. this corresponds to sonet speci?ation that it will take two consecutive valid framing patterns to frame to an incoming signal. outside the ?of state, the oof alarm output is low. figure 19. transmit clocking diagram in sonet mode pat_srch reset oof=1 patdet & !ffm new_frm in_frm patdet patdet oof=0 !patdet oof_one oof_two oof_three legend: ffm ~ in fast frame mode and ffm and ffm !ffm and patdet !patdet patdet !patdet patdet !patdet !patdet !ffm ~ in regular frame mode patdet ~ correct 4a1/4a2 framing pattern detected !patdet ~ correct 4a1/4a2 framing pattern not detected !patdet !patdet patdet
lattice semiconductor orca orso42g5 and orso82g5 data sheet 35 section (b1) bip-8 calculator the section bip-8 b1 byte in a given sts-n frame contains the scrambled bip value for all scrambled bytes of the previous frame. except for the a1,a2 and j0 section overhead bytes, all bytes in a frame are scrambled. the sec- tion (b1) bip-8 is calculated as the even parity of all bits in the current sts-48 frame. this value is compared to the section overhead b1 byte of the next frame. b1 error counters are available that monitors the number of b1 errors on a per-channel basis. a b1 parity error ?g is also generated as a software alarm bit. descrambler the data from the framer is descrambled using the sonet/sdh standard generator polynomial 1 + x 6 + x 7 . the descrambling is performed in parallel on each 32-bit word per channel, synchronized to the frame pulse and can be disabled through the software register bit. rdi (remote defect indicator) monitor the line rdi (rdi-l) is monitored through bits 2-0 of the k2 byte. within the 32-bit descrambled data, a pattern of ?10 on bits 26-24 will indicate a rdi-l status. rdi-l must be detected in two consecutive frames before an rdi alarm register bit is set. if fast_frame_mode is enabled, then the rdi alarm register bit will be set if rdi-l is detected in one frame. receive fifo clock domain transfers and multi-link de-skew are one of the most critical parts of this device. the main clock domain transfer for the datapath is handled by the receive fifo. for each link, there are two fifos. a 24 x 33 fifo is used in sonet mode. the use of the fifo is controlled by con?uration bits. data can be sent from the descrambler directly to the fpga bypassing the alignment fifo. data from each channel will have an associated clock (rwckxx at 77.76 mhz). each channel will also provide a fp and spe indicator along with the data. descrambling can be inhibited through the dscr_inh_xx control bit. data can be sent directly from the 8:32 demux block to the fpga bypassing the alignment fifo and sonet framer and descrambler. data from each channel will have an associated clock. no spe or fp indicator is pro- vided with the data. receive fifo in sonet mode the receive fifo used in sonet mode will allow for an inter-link skew of about 300 ns (24 x 32 = 768 bits, 400 ps per bit gives 307 ns). the fifo is written at 77.76 mhz and read at 77.76 mhz. once frame synchronization has occurred, the write control logic will cause data to be written to the memory. the write control block is required to insure that the word containing the ?st a1 byte is written to the same location (address 0) in the fifo. the syn- chronization algorithm issues a sync pulse and sync error signals to the read control block based on the alignment option chosen. this sync pulse will coordinate the reading of the fifos. the read control logic synchronizes the reading of the fifo for the streams that are to be aligned. the block begins reading when the fifo sync sub block signals that all of the applicable a1s with the appropriate margin have been written to the fifo. all of the read blocks to be synchronized begin reading at the same time and same location in the memory (address 0). the block also takes the difference between the write and read address to indicate the rel- ative skews between the links. if this difference exceeds a certain limit (programmable), then an alarm (alignment over?w) is provided to the register interface. multi-channel alignment in sonet mode ?orso42g5 the alignment fifo allows the transfer of all data to a common clock. the fifo sync block allows the system to be con?ured to allow the frame alignment of multiple slightly varying data streams. this optional alignment ensures that matching serdes streams will arrive at the fpga end in perfect data sync. it is important to note that for all aligned channels in a group, the serdes transmitters on the other side of the high-speed link must all be transmit- ting data at exactly the same frequency (0 ppm difference), i.e., using a common clock source. the orso42g5 has a total of four channels (two per serdes block). the incoming data of these channels can be synchronized in several ways, or they can be independent of one other. two channels within a serdes can be
lattice semiconductor orca orso42g5 and orso82g5 data sheet 36 aligned together, channels c and d to form a pair as shown in figure 20. alternately, all four channels in the ser- des blocks can be aligned together to form a communication channel with a bandwidth of 10 gbits/s as shown in figure 21. figure 20. twin channel alignment ?orso42g5 figure 21. quad channel alignment of serdes blocks a and b ?orso42g5 individual channels within an alignment group can be disabled (i.e., powered-down) without disrupting other chan- nels. note that the serdes channel that is powered down can not be the source of the rsysclkxx that is clock- ing the read side of the alignment fifo. when a disabled channel becomes active as part of an alignment group, the group may need to be re-aligned. then the whole group needs to be resynched. this would only need to occur if the transmitting frame pulse for the new link is different from the rest of the group. each channel is provided with a 24 word x 33-bit fifo. the fifo can perform two tasks: (1) to change the clock domain from receive clock to a clock from the fpga side, and (2) to align the receive data over 2 or 4 channels. this fifo allows a timing budget of 307 ns that can be allocated to skew between the data lanes and for transfer to the common clock. the input to the fifo consists of 32-bit data and a frame pulse that indicates the start of a frame (or a1a2 framing bytes). this frame pulse is used to synchronize multiple channels within an alignment group. if a channel is not in any alignment group, the fifo control logic will set the fifo-write-address to the beginning of the fifo, and will set the fifo-read-address to the middle of the fifo at the ?st assertion of frame pulse after reset or after the resync command. the rx_fifo_min register bits can be used to control the threshold for minimum unused buffer space in the align- ment fifos between read and write pointers before ovfl status is ?gged. the synchronization algorithm con- sists of a down counter which starts to count down by 1 from its initial value of 18 (decimal) when a frame pulse from any channel within an alignment group has been received. the oos alarm indicates the fifo is out-of sync and the channel skew exceeds that which can be handled by the fifo. once the frame pulse for all channels within the alignment group have been received, the count is decremented by 2 until 0 is reached. data are then read from the fifos and output to the spe generator before being sent to the fpga. for every alignment group, there is an ovfl and oos status register bit. the oos bit is ?gged when the down counter in the synchronization algorithm has reached a value of 0 and frame pulse from all channels within an alignment group have not been received. the ovfl bit is ?gged when the read address at the time of receiving a channel ac channel ad channel bc channel bd channel ac channel ad t 0 t 1 of channels ac and ad twin alignment twin alignment of channels bc and bd channel bc channel bd channel ac channel ad channel bc channel bd channel ac channel ad channel bc channel bd t 0 quad alignment of channels ac , ad , bc , and bd
lattice semiconductor orca orso42g5 and orso82g5 data sheet 37 frame pulse, is less than the minimum threshold set by rx_fifo_min. in the memory map section oos is referred to as sync2_[a2,b2]_oos, sync4_oos. ovfl is referred to as sync2_[a2,b2]_ovfl, sync4_ovfl. receive clocking for multi-channel alignment ?orso42g5 there are a total of seven clocks for the receive path, from fpga to the core. the two used in sonet mode are rsysclka2 (for block a), and rsysclkb2 (for block b). the following diagrams show the recommended clock distribution approaches for sonet mode multi-channel alignment modes. cell mode alignment is discussed in the section describing the input port controller (ipc).) sonet mode twin alignment ?orso42g5 figure 22 describes the clocking scheme for twin alignment. in twin alignment, the valid channel pairs are ac,ad in block a and bc,bd in block b. the ?ure provides the clocking scheme for block a as an example. rsysclka2 should be sourced from rck78a, rwckac or rwckad. for the orso42g5, the use of rck78a is recom- mended since it uses primary clock routing resources. this clocking approach provides the required 0 ppm clock frequency matching for each pair and provides ?xibility in applications where the two pairs are received from asyn- chronous sources. figure 22. receive clocking diagram for twin alignment in block a ?orso42g5 sonet mode quad alignment ?orso42g5 figure 23 shows the clocking scheme for four-channel alignment. in this application, both clocks rsysclka2 and rsysclkb2 should be sourced from a common clock. either rck78a or rck78b can be used as a common clock source. the ?ure shows rck78a being used as the clock source. serdes 2.488 gbits/s demux rwckac (77.76 mhz) fpga rwckad rck78a alignment spe generator rsysclka2 framer , descrambler logic common to block refclka[p,n] (155.52 mhz) channel ac channel ad hdin[p:n]_ac serdes 2.488 gbits/s hdin[p:n]_ad demux alignment spe generator framer , descrambler rwckad fifo fifo
lattice semiconductor orca orso42g5 and orso82g5 data sheet 38 figure 23. receive clocking diagram for sonet mode quad-channel alignment in block a ?orso42g5 multi-channel alignment in sonet mode (orso82g5) the alignment fifo allows the transfer of all data to a common clock. the fifo sync block allows the system to be con?ured to allow the frame alignment of multiple slightly varying data streams. this optional alignment ensures that matching serdes streams will arrive at the fpga end in perfect data sync. it is important to note that for all aligned channels in a group, the serdes transmitters on the other side of the high-speed link must all be transmit- ting data at exactly the same frequency (0 ppm difference), i.e., using a common clock source. the orso82g5 has a total of eight channels (four per serdes block). the incoming data of these channels can be synchronized in several ways, or they can be independent of one other. two channels within a serdes can be aligned together; channel a and b and/or channel c and d can form a pair as shown in figure 24. alternately, all four channels in a serdes block can be aligned together to form a communication channel with a bandwidth of 10 gbits/s as shown in figure 25. finally, the alignment can be extended across the serdes blocks to align all eight channels in the orso82g5 as shown in figure 26. individual channels within an alignment group can be disabled (i.e., powered-down) without disrupting other channels. note that the serdes channel that is powered down can not be the source of the rsy- sclkxx that is clocking the read side of the alignment fifo. when a disabled channel becomes active as part of an alignment group, the group may need to be re-aligned. then the whole group needs to be resynched. this would only need to occur if the transmitting frame pulse for the new link is different from the rest of the group. fpga rck78a rwckad rwckbc rwckbd rwckac spe generator spe generator spe generator spe generator alignment fifo alignment fifo alignment fifo alignment fifo framer, descrambler framer, descrambler framer, descrambler framer, descrambler logic common to block common 155.52 mhz serdes demux rsysclka2 channel ac channel ad hdin[p:n]_ac 2.488 gbits/s serdes hdin[p:n]_ad 2.488 gbits/s demux serdes demux rsysclkb2 channel bc channel bd hdin[p:n]_bc 2.488 gbits/s serdes hdin[p:n]_bd 2.488 gbits/s demux refclka[p,n] refclkb[p ,n]
lattice semiconductor orca orso42g5 and orso82g5 data sheet 39 figure 24. twin channel alignment ?orso82g5 figure 25. alignment of serdes blocks a and b ?orso82g5 figure 26. alignment of all eight serdes channels ?orso82g5 each channel is provided with a 24 word x 33-bit fifo. the fifo can perform two tasks: (1) to change the clock domain from receive clock to a clock from the fpga side, and (2) to align the receive data over 2, 4, or 8 channels. this fifo allows a timing budget of 307 ns that can be allocated to skew between the data lanes and for transfer to the common clock. the input to the fifo consists of 32-bit data and a frame pulse that indicates the start of a channel ab channel ac channel ad channel ba channel bb channel bc channel bd channel aa channel ab channel ac channel ad channel ba channel bb channel bc channel bd t 2 channel aa t 1 t 0 t 3 twin alignment of channels aa and ab twin alignment of channels ac and ad twin alignment of channels ba and bb twin alignment of channels bc and bd channel ab channel ac channel ad channel ba channel bb channel bc channel bd channel aa channel ab channel ac channel ad channel ba channel bb channel bc channel bd t 1 t 0 channel aa block alignment of channels aa , ab , ac , and ad block alignment of channels ba , bb , bc , and bd channel aa channel ab channel ac channel ad channel ba channel bb channel bc channel bd channel aa channel ab channel ac channel ad channel ba channel bb channel bc channel bd t 0
lattice semiconductor orca orso42g5 and orso82g5 data sheet 40 frame (or a1a2 framing bytes). this frame pulse is used to synchronize multiple channels within an alignment group. if a channel is not in any alignment group, the fifo control logic will set the fifo-write-address to the beginning of the fifo, and will set the fifo-read-address to the middle of the fifo at the ?st assertion of frame pulse after reset or after the resync command. the rx_fifo_min register bits can be used to control the threshold for minimum unused buffer space in the align- ment fifos between read and write pointers before ovfl status is ?gged. the synchronization algorithm con- sists of a down counter which starts to count down by 1 from its initial value of 18 (decimal) when a frame pulse from any channel within an alignment group has been received. the oos alarm indicates the fifo is out-of sync and the channel skew exceeds that which can be handled by the fifo. once the frame pulse for all channels within the alignment group have been received, the count is decremented by 2 until 0 is reached. data are then read from the fifos and output to the spe generator before being sent to the fpga. for every alignment group, there is an ovfl and oos status register bit. the oos bit is ?gged when the down counter in the synchronization algorithm has reached a value of 0 and frame pulse from all channels within an alignment group have not been received. the ovfl bit is ?gged when the read address at the time of receiving a frame pulse, is less than the minimum threshold set by rx_fifo_min. in the memory map section oos is referred to as sync[2,4]_[a1,a2,b1,b2]_oos, sync8_oos. ovfl is referred to as sync[2,4]_[a1,a2,b1,b2]_ovfl, sync8_ovfl. receive clocking for multi-channel alignment ?orso82g5 there are a total of nine clocks for the receive path, from fpga to the core. the four used in sonet mode are rsysclka1 and rsysclka2 (both for block a), and rsysclkb1 and rsysclkb2 (both for block b). the fol- lowing diagrams show the recommended clock distribution approaches for sonet mode multi-channel alignment modes. cell mode alignment is discussed in the section describing the input port controller (ipc).) sonet mode twin alignment figure 27 describes the clocking scheme for twin alignment in the orso82g5. in twin alignment, the valid channel pairs are aa,ab and ac,ad in block a and ba,bb and bc,bd in block b. the ?ure provides the clocking scheme for block a as an example. rsysclka1 should be sourced from rwckaa or rwckab. rsysclka2 should be sourced from rwckac or rwckad. this clocking approach provides the required 0 ppm clock frequency match- ing for each pair and provides ?xibility in applications where the two pairs in the block are received from asynchro- nous sources or operate at different rates.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 41 figure 27. receive clocking diagram for twin alignment in block a ?orso82g5 serdes 2.488 gbits/s demux rwckaa (77.76 mhz) fpga other links in block rck78a alignment spe generator rsysclka1 framer , descrambler logic common to block refclka[p,n] (155.52 mhz) channel aa channel ab hdin[p:n]_aa serdes 2.488 gbits/s hdin[p:n]_ab demux alignment spe generator framer , descrambler rwckab fifo fifo
lattice semiconductor orca orso42g5 and orso82g5 data sheet 42 sonet mode block alignment ?orso82g5 figure 28 describes the clocks and recommended clocking for block alignment in the sonet mode. for block alignment, the low speed portion for each block should be sourced by a single clock. as the ?ure shows, for block a, rsysclka1 and rsysclka2 should be sourced by rck78a. for block b, rsysclkb1 and rsysclkb2 should be sourced by rclk78b. rclk78a can be sourced by any channel in block a and rclk78b can be sourced by any channel in block b. figure 28. receive clocking diagram for four-channel alignment in block a ?orso82g5 sonet mode octal alignment ?orso82g5 figure 29 shows the clocking scheme for eight-channel alignment. in this application, all four clocks rsysclka1, rsysclka2, rsysclkb1 and rsysclkb2 should be sourced from a common clock. either rck78a or rck78b can be used as a common clock source. the ?ure shows rck78a being used as the clock source. fpga rck78a spe generator spe generator spe generator spe generator alignment fifo alignment fifo alignment fifo alignment fifo framer, descrambler framer, descrambler framer, descrambler framer, descrambler demux rsysclka1 logic common to block refclka[p,n] (155.52 mhz) channel aa channel ab hdin[p:n]_aa 2.488 gbits/s hdin[p:n]_ab 2.488 gbits/s rsysclka2 channel ac channel ad rwckad rwckaa hdin[p:n]_aa 2.488 gbits/s hdin[p:n]_ab 2.488 gbits/s serdes demux serdes demux serdes demux serdes
lattice semiconductor orca orso42g5 and orso82g5 data sheet 43 figure 29. receive clocking diagram for sonet mode eight-channel alignment ?orso82g5 serdes demux fpga rck78a rwckaa rwckab rwckad rwckbb rwckbc rwckbd rwckba rwckac spe generator spe generator spe generator spe generator spe generator spe generator spe generator spe generator alignment fifo alignment fifo alignment fifo alignment fifo alignment fifo alignment fifo alignment fifo alignment fifo framer, descrambler framer, descrambler framer, descrambler framer, descrambler framer, descrambler framer, descrambler framer, descrambler framer, descrambler rsysclka1 logic common to bloc k common 155.52 mhz channel aa channel ab hdin[p:n]_aa 2.488 gbits/s serdes hdin[p:n]_ab 2.488 gbits/s demux serdes demux rsysclka2 channel ac channel ad hdin[p:n]_ac 2.488 gbits/s serdes hdin[p:n]_ad 2.488 gbits/s demux serdes demux rsysclkb1 channel ba channel bb hdin[p:n]_ba 2.488 gbits/s serdes hdin[p:n]_bb 2.488 gbits/s demux serdes demux rsysclkb2 channel bc channel bd hdin[p:n]_bc 2.488 gbits/s serdes hdin[p:n]_bd 2.488 gbits/s demux refclka[p,n] refclkb[p ,n]
lattice semiconductor orca orso42g5 and orso82g5 data sheet 44 spe generator the spe generator in the orso42g5 and orso82g5 is used to indicate the payload and overhead portions of a sonet frame. it is present in the sonet data path only. the spe generator generates row, column and sts counters based on the frame pulse received from the (24 x 33) alignment fifo or from the descrambler if align- ment fifos are bypassed. it also retimes the 32-bit data in order to align it with the spe indicator. the spe gener- ator will also detect negative or positive pointer justi?ation (if justi?ation is enabled) by looking at the id bits in the h1 and h2 bytes and adjust the spe indicator for the sts-1 frame being justi?d as follows: during positive pointer justi?ation, the spe will be low during h3 byte and the spe byte following it. during negative pointer justi?ation, the spe will be high during h3 byte. during no justi?ation, the spe will be low during h3 byte. this block only detects the incoming pointer bytes for spe generation. this capability can be enabled by software control. by default, the spe generator will ignore any pointer justi?ation. this block has no capability of any pointer processing, pointer checking or pointer mover operation and ignores ?ew data indications from the sonet speci?ation. sonet mode receive timing ?orso42g5 this section contains timing diagrams for major interfaces of this block to the fpga logic when sonet frames are to be transferred. when operating in sonet mode, the entire sonet frame is sent to the fpga. in multi-channel alignment mode(s), data from all channels within an alignment group are aligned to the a1a2 framing bytes. each sonet frame is 125 s. the frame starts with 36 clock cycles (77.76 mhz) of toh followed by 1044 clock cycles of spe, followed by 36 clock cycles of toh, 1044 cycles of spe. the doutxx_spe signal indicates toh or spe in the data (low for toh, high for spe) twin pairs are ac, ad (group a2) and bc, bd (group b2) figure 32 shows the sonet twin alignment mode timing for the orso42g5. the frame pulse and spe indicators are show for each of the two channels (ac, ad) in twin alignment. figure 30. receive clocking diagram for sonet mode twin alignment in block a ?orso42g5 rsysclka2 doutac[31:0] doutac_fp tttttsss s ssttttt tttt ssss s ... 1 cycle 36 cycles toh 1 044 cycles spe 36 cycles toh start of fr ame 125 s data t represents toh s represents spe doutxx-spe is high for spe, low for toh clocks rsysclka2 is the read clock used for group a2 rsysblkb2 is the read clock used f or group b2 36 cycles to h tttttsss s ssttttt tttt ssss s start of fr ame doutac_spe doutad[31:0] doutad_spe dout ad_fp
lattice semiconductor orca orso42g5 and orso82g5 data sheet 45 figure 31 shows the quad alignment mode in the orso42g5. figure 31. receive sonet mode, quad alignment mode ?orso42g5 sonet mode receive timing ?orso82g5 this section contains timing diagrams for major interfaces of this block to the fpga logic when sonet frames are to be transferred. when operating in sonet mode, the entire sonet frame is sent to the fpga. in multi-channel alignment mode(s), data from all channels within an alignment group are aligned to the a1a2 framing bytes. each sonet frame is 125 s. the frame starts with 36 clock cycles (77.76 mhz) of toh followed by 1044 clock cycles of spe, followed by 36 clock cycles of toh, 1044 cycles of spe. the doutxx_spe signal indicates toh or spe in the data (low for toh, high for spe) twin pairs are aa, ab (group a1), ac, ad (group a2), ba, bb (group b1) and bc, bd (group b2) figure 32 shows the sonet twin alignment mode timing for the orso82g5. the frame pulse and spe indicators are show for each of the two channels (aa, ab) in twin alignment. figure 32. receive clocking diagram for sonet mode twin alignment in block a ?orso82g5 ... 1 cycle 36 cycles toh 1044 cycles spe 36 cycles toh start of frame 125 s clocks rsysclka2 and rsysysclkb2 are sourced b y rck78a 36 cycles toh start of frame doutac_fp doutad_fp rsysclk[a2,b2 ] doutbc_fp doutbd_fp rsysclka1 doutaa[31:0] doutaa_fp tttttsss s ssttttt tttt ssss s ... 1 cycle 36 cycles toh 1 044 cycles spe 36 cycles toh start of frame 125 s data t represents toh s represents spe doutxx-spe is high for spe, low for toh clocks rsysclka1 is the read clock used for group a1 rsysclka2 is the read clock used for group a2 rsysclkb1 is the read clock used for group b1 rsysblkb2 is the read clock used for group b2 36 cycles toh tttttsss s ssttttt tttt ssss s start of frame doutaa_spe doutab[31:0] doutab_spe doutab_fp
lattice semiconductor orca orso42g5 and orso82g5 data sheet 46 figure 33 shows the sonet quad alignment mode in the orso82g5. figure 33. receive clocking diagram for sonet mode quad alignment ?orso82g5 only frame pulse (doutxx_fp) and clocks are shown for understanding of block alignment. timing of data and spe indicators are the same as shown for twin alignment. block groups are group a - aa,ab,ac,ad and group b - ba,bb,bc,bd figure 34 shows the octal alignment mode in the orso82g5. figure 34. receive sonet mode?ctal alignment mode ?orso82g5 rsysclk[a1,a2 ] doutaa_fp ... 1 cycle 36 cycles toh 1044 cycles spe 36 cycles toh start of frame 125 s clocks rsysclka1 and rsysclka2 are sourced by rck78a 36 cycles toh start of frame doutab_fp doutac_fp doutad_fp rsysclk[a1,a2 ] rsysclk[a1,a2 ] doutaa_fp ... 1 cycle 36 cycles toh 1044 cycles spe 36 cycles toh start of frame 125 s clocks rsysclka1, rsysclka2, rsysclkb1, and rsysysclkb2 are sourced by rck78a 36 cycles toh start of frame doutab_fp doutac_fp doutad_fp rsysclk[b1,b2 ] doutba_fp doutbb_fp doutbc_fp doutbd_fp
lattice semiconductor orca orso42g5 and orso82g5 data sheet 47 orso42g5 con?uration at startup, the legacy serdes channel logic must be powered down and removed from any multi-channel align- ment groups: setting bit 1 to one in registers at locations 30002, 30012, 30102 and 30112 powers down the legacy logic. (note that the reset value for these bits is 0.) setting bit 1 to zero (reset condition) in the register at locations 30802, 30812, 30902 and 30912 removes the legacy logic from any alignment group. register settings for sonet multi-channel alignment are shown in table 7. table 7. multichannel alignment modes ?orso42g5 to align two channels in serdes a: fmpu_synmode_ac = 01 (register location 30822) fmpu_synmode_ad = 01 (register location 30832) to align two channels in serdes b: fmpu_synmode_bc = 01 (register location 30922) fmpu_synmode_bd = 01 (register location 30932) to align all four channels: fmpu_synmode_ac = 11 (register location 30822) fmpu_synmode_ad = 11 (register location 30832) fmpu_synmode_bc = 11 (register location 30922) fmpu_synmode_bd = 11 (register location 30932) to enable/disable multi-channel alignment of individual channels within a multi-channel alignment group: fmpu_str_en_xx = 1 enabled fmpu_str_en_xx = 0 disabled where xx = [ac,ad,bc,bd] to resynchronize a multichannel alignment group set the following bits to one, and then set to zero: fmpu_resync4 for four channels, ac, ad, bc and bd. (register location 30a04, bit 7) fmpu_resynca2 for dual channels, ac and ad. (register location 30a04, bit 2) fmpu_resyncb2 for dual channels, bc and bd. (register location 30a04, bit 5) to resynchronize an independent channel (resetting the write and the read pointer of the fifo) set the following bits to one, and then set to zero. fmpu_resync1_xx (register locations 30824, 20834, 30924 and 30934, bit 7) where xx is one of ac, ad, bc or bd. register bits fmpu_synmode_xx[2:3] mode 00 no multichannel alignment 01 twin channel alignment 11 four channel alignment note: xx = [ac,ad,bc,bd]
lattice semiconductor orca orso42g5 and orso82g5 data sheet 48 alignment mode setup procedures ?orso82g5 the control register bits for alignment fifo in the orso42g5 and orso82g5 are described below. table 8. multichannel alignment modes ?orso82g5 to align all eight channels: fmpu_synmode_a[a:d] = 11 fmpu_synmode_b[a:d] = 11 to align twin channels in serdes a: fmpu_synmode_a[a:d] = 01 to align four channels in serdes a: fmpu_synmode_ab = 10 fmpu_synmode_ad = 10 similar alignment can be de?ed for serdes b. to enable/disable synchronization signal of individual channel within a multi-channel alignment group: fmpu_str_en_xx = 1 enabled fmpu_str_en_xx = 0 disabled where xx is one of a[a:d] and b[a:d]. to re-synchronize a multi-channel alignment group set the following bit to zero, and then set it to 1 since it is a rising edge sensitive bit. fmpu_resync8 for eight channel a[a:d] and b[a:d] fmpu_resync4a for block channel a[a:d] fmpu_resync2a1 for twin channel a[a:b] fmpu_resync2a2 for twin channel a[c:d] fmpu_resync4b for block channel b[a:d] re-synchronization will cause the multi-channel alignment group to perform a new synchronization procedure. this would need to occur if a link is removed from an alignment group and then paced back into service as part of the alignment group. this is not required at power up if the alignment mode is set before the channels receive the ?st frame pulse. register bits fmpu_synmode_xx mode 00 no multichannel alignment. (default) 01 twin channel alignment 10 block channel alignment 11 eight channel alignment note: where xx is one of a[a:d] and b[a:d].
lattice semiconductor orca orso42g5 and orso82g5 data sheet 49 cell mode detailed description a common application for the orso42g5 and orso82g5 is to provide a bridge between a port card and a cell- based switch fabric. in cell mode, the data in the synchronous payload envelope (spe) of the sonet frames is further formatted into ?ed-length cells by the orso42g5 and orso82g5. the cell contents will typically be unique to speci? port card and switch devices. the orso42g5 and orso82g5 supports this application with a ?ell mode of operation the basic data ?ws in cell mode are shown in figure 35. data to be transmitted is received from the fpga logic (see table 11 and table 12 for details of the core/fpga signal assignments in the transmit direction which differ signi?antly from the serdes only and sonet modes), inserted into the spe of the sonet frame, scrambled and transmitted from the serdes block. in cell mode, multiple serdes links are used to achieve desired band- width. a two-link mode is supported in the orso42g5 and both two-link and eight-link cell modes are supported. for such interfaces, data are cell-striped in a round-robin fashion across multiple links by the transmitter. figure 35. basic data flows - cell mode in the receive direction, the framed data are received from the serdes block, descrambled and are passed into a cell extractor which extracts individual cells from the payload portion of the sonet frame. the cells are then passed through a fifo that performs lane-to-lane deskew and a clock domain transfer. the clock domain transfer is handled automatically using idle cell insertion and deletion. the cells are passed into either the eight-link input port controller ipc8 block (orso82g5 only) or to one of the two-link ipc2 block(s), which reassemble the cells back into a single cell stream (destriping) which is sent to the fpga logic. (see table 13 and table 14 for details of the core/fpga signal assignments in the receive direction. as with the transmit path, the cell mode assignments differ signi?antly from those for the serdes only and sonet modes). serdes and sonet processing has been described in previous sections and only features unique to the cell mode will be discussed in the following sections. the cell format will be discussed ?st, followed by a description of the transmit path, which will include either a two-link or an eight-link output port controller (opc) block, and a description of the receive path, including the two-link or eight-link input port controller (ipc) blocks. cell formats cells are arranged within a sonet (sts-48c) frame as shown in figure 36. a sonet sts-48c frame has 4176 (87 x 48) columns of spe and 9 rows that gives a total of 37,584 bytes. in this implementation, data in a spe is lim- ited to ?ed size cells. though four cell sizes are supported, only one cell size can be used at a time. user i/o receive (rx) path transmit (tx) path configurable as four or eight data channels organized in two blocks mux/demux & serdes orca 4e04 fpga logic configurable cell processing pseudo- sonet processing mux/demux and serdes
lattice semiconductor orca orso42g5 and orso82g5 data sheet 50 figure 36. cell mapping in sonet frame the cells are placed in a sonet frame such that the ?st cell starts at the ?st spe column of the ?st row (145th column. 144 columns are taken up by toh). subsequent cells are placed contiguously, skipping the transport overhead (toh) columns when appropriate. the orso42g5 and orso82g5 supports four cell sizes with varying payloads. the total cell size sent across the backplane is the combined size of the user cell payload (cell header and data), user bip and the link header byte. table 9 indicates the cell sizes supported by the orso42g5 and orso82g5 within a sts-48c frame. only one cell size can be used at a time. table 9. orso42g5 and orso82g5 supported cell sizes a cell cannot span multiple sonet frames. this implies that there may be some cell sizes for which some bytes will be unused at the end of a spe. these are called pad bytes. each cell is preceded by a link header byte as shown in figure 37. table 10 de?es the format of the link header. the link header byte is useful for cell delineation when cell data are striped across multiple links. the link header is inserted automatically in the transmit direction by the ipc block. the link header is checked in the receive direc- tion and removed by the opc before the cell is sent across the core/fpga interface. total cell size (across b/p) user cell payload size (header/data) link header byte user bip field cells/frame number of pad bytes per spe 77 75 1 1 488 8 81 79 1 1 464 0 85 83 1 1 442 14 93 91 1 1 404 12 note: to calculate the number of cells per spe: [(87rows/sts-1*9columns/sts-1)octets/(sts-1 spe)] * 48 sts-1 = 37584 octets 337584 / total cell size = # of cells per spe. toh bytes a1 a2 j0 cell 0 cell 1 cell 2 (etc.) link header byte pad bytes bytes cell payload
lattice semiconductor orca orso42g5 and orso82g5 data sheet 51 figure 37. link header byte table 10. link header format in cell mode, multiple serdes links are used to achieve desired bandwidth. data are cell-striped in a round-robin fashion across two or eight links by the transmitter and then re-assembled back into a single cell stream (destrip- ing) by the receiver. this is shown in figure 38. figure 38. multi-link interface - two-link example to assist with cell delineation, each link transmitter assigns sequence numbers to cells (lseqn[6:0] bits in the link header byte) before sending them out on the link. each link increments its sequence numbers independently as shown in figure 38. all links reset their sequence number generator at the beginning of a sonet frame (all links are synchronized to the start of a frame). on the receiving side, each receiver uses the sequence numbers to verify the correct cell delineation. since the links were synchronized to the start of the sonet frame, all links will have cells with the same sequence number available at the same time (although deskew needs to happen to properly align the cells). this allows the receiver to correctly reconstruct the original cell stream. if an unexpected sequence number is received, the receiver does not use the received value as the basis for the next expected sequence number. rather the old expected value is incremented by one, forming the new expected value. an error ?g is sent to the software register interface and the cell will be marked with an error. for example, assume that the receiver expected to receive a cell with sequence number 27, but received one with sequence number 37. the cell will be marked with an error. the receiver then expects to receive a cell with sequence number 28. location field/description 7 idle: idle cell indicator 0: user cell (contains valid data) 1: idle cell (no data in the cell payload) 6:0 lseq: link sequence number. this value is used when aligning cells from multiple links when doing link group multiplexing. lidle lseqn[6:0] link header byte time transmitter time 3 2 1 0 7 6 5 4 cell striping 0 1 lseq = 3 cell = 7 lseq = 2 cell = 5 lseq = 1 cell = 3 lseq = 0 cell = 1 time receiver 3 2 1 0 7 6 5 4 cell de-striping 0 1 lseq = 3 cell = 6 lseq = 2 cell = 4 lseq = 1 cell = 2 lseq = 0 cell = 0
lattice semiconductor orca orso42g5 and orso82g5 data sheet 52 there is no way to tell where a cell starts unless one counts the cells from the beginning of the spe. that means, there is no way to regain lost cell delineation other than wait for the next sonet frame. cell mode transmit path in the transmit path in cell mode, the transmit logic creates a sonet-like transport frame for the data, adds the required transport overhead bytes (cell mode automatically uses auto_toh mode) and retimes the cell data from the fpga interface rate of 156 mhz to the framer rate of 77.76 mhz. the data are then sent to the sonet logic blocks and serdes. the payload sub-block of the sonet logic operates somewhat differently than in sonet mode, however. output port controller the orso42g5 has two link controllers (opc2s). in cell mode the output port controller (opc) is the block responsible for directing traf? for the transmit traf? ?w. there are four two-link controllers and one eight-link con- troller (opc8) in the orso82g5. the user provides 160-bit data (opc8) or 40-bit data (opc2s) at 156 mhz, along with a cell valid strobe from the fpga logic. no link header byte is sent with the cell data. the opc provides the following functions: accepts cell payload from the fpga logic and assembles legal output cells from these. inserts bit interleaved parity (bip) schedules, manages and performs writes of cell data into tx fifos in the transmit framer blocks of all the eight- links or up to 4 pairs of two-links. provides backpressure information to the fpga to stop writes to the txfifo if the fifo is not ready to accept data. the opc blocks, shown in figure 39, operate as follows: opc8 to stripe cells across eight links (orso82g5 only) opc2_a1 to service links aa,ab (orso82g5 only) opc2_a2 to service links ac,ad opc2_b1 to service links ba,bb (orso82g5 only) opc2_b2 to service links bc,bd when operating with some links in the two-link cell mode, links not in an alignment group can optionally be oper- ated in sonet and/or serdes-only modes.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 53 figure 39. opc2 and opc8 block diagrams tx fifo block in cell mode, the txfifo block contains the write state machine and fifo memory. the fifo is used to retime the cell data from the fpga interface at a rate of 156 mhz to the framer rate of 77.76 mhz. the fifo memory is implemented as a 64 x 34 fifo. the fifo receives data as 33-bit words with the start-of-cell as the msb of each word. thus each cell occupies a maximum size of 23 words. for each link, the memory must be capable of holding at least 2 cells or 46 words (one for write and one for read). to ensure extra space, this capacity has been increased to 64 words. in addition, an extra bit has been reserved to store the link idle cell indi- cator bit which is used for indicating the internally generated idle cells. thus each word in a cell is 34 bits. data are written to the memory on the 156 mhz clock domain and read on the 77.76 mhz clock domain by the tx_frame_processor block. the opc requires no response from the txfifo for writing data. the txfifo is guar- anteed by design to not over?w or underrun with correct clocking. tx frame processor the tx_frame_processor (tfp) block is the primary data processing block in the both sonet mode and cell mode. it organizes the cell data into a sonet frame before sending it to the serdes. in cell mode, the 32-bit data comes from the tx fifo block. the three major tfp sub-blocks were described in the sonet mode section. in cell mode, the payload sub block is activated by the link_frm_sync in cell mode. a pulse on this signal from the opc indicates the start of a frame. each frame contains 4 different types of bytes in cell mode: toh bytes (auto toh mode only) link header (lh) bytes cell payload bytes pad bytes tx fifo opc2 block opc2_[a:b][1:2][39:0] sysclk156[a:b][1:2] 32 77.76 mhz tx fifo 32 77.76 mhz tx fifo opc8 opc8[159:0] sysclk156 8 32 77.76 mhz tx fifo 32 77.76 mhz link 0 link 1 link 0 link 7 40 160 fpga logic block fpga logic (orso82g5 only)
lattice semiconductor orca orso42g5 and orso82g5 data sheet 54 there are n x 3 (n = 48) bytes of toh per row and there are a total of 9 rows in a sonet frame. in cell mode, the rest of the bytes in each row after the toh bytes are ?led by cells. the ?st byte in a cell is a link header (lh) byte. at the end of each frame, there are pad bytes if required. an important function of the payload block is the grouping of bytes together to be presented to the scramble logic. due to the insertion of the lh byte in each cell, the total cell data are not divisible by 4 (4 bytes are sent per 77.76 mhz clock cycle). at the end of each row within a sonet frame, the payload block stops sending cell data and indicates to the toh block to insert the next rows toh bytes. at the end of the toh byte transmission, the cell data transmission is resumed. at the end of a cell, the cells bip-8 byte is inserted. the next cells link header byte (lh) immediately follows the previous cells bip-8 byte. the msb of the lh byte is the link idle cell indicator bit. the payload block gets this bit from the msb of the ?st word of a cell in the memory and inserts it into the lh byte for the appropriate cell. the rest of the lh byte is the link sequence number. this number is incremented for each subsequent cell. after all cells have been transmitted, the appropriate number of pad bytes are sent. at a link speed of 2.5 ghz, there are 38,880 bytes (spe + toh) per frame. there are 1296 bytes of toh and 37,584 bytes of spe. for cell data of 85 bytes this translates to 442 cells per frame and 14 pad bytes (# of cells per frame = # of bytes of spe/# of bytes in a cell). cell mode transmit timing figure 40 shows the transmit clocks and recommended clocking scheme in cell mode. tck156a, tck157b can be used as a 156 mhz clock source for sysclk156[a1, a2] and sysclk156[b1, b2] respectively. sysclk156[a1, a2] and sysclk[b1, b2] are shared with the receive logic in cell mode. figure 40. cell mode transmit timing when operating in the two-link cell mode, each opc2 block passes cells from fpga to embedded core. depending upon the con?ured cell size, cell transfers will take a variable number of sysclk156 cycles to be transmitted across the interface. data are always transferred across a 40-bit bus (5 octets per clock cycle). figure 41 shows 16 clock cycles for a cell transfer this corresponds to a cell size of 79 octets. the two control sig- nals in the ?ure are de?ed as: cell_begin_ok: cell request signal from core to fpga. it will be asserted every 20 or 16 clock cycles (depending on cell size) when the core is ready to accept cells from fpga. opc2 payload txfifo fpga cell data tck78a sysclk156[a:b][1:2] cell valid backpressure signal tck156a or sysclk568 block tsysclkxx logic common to each block cell data cell valid backpressure signal sdo_bp_8 opc8_cellvalid opc2_[a:b][1:2][39:0] cell_begin_ok_[a:b][1:2] opc8 [159:0] opc2_[a:b][1:2]_cellvalid opc2 opc8 (orso82g5 only) or opc8 (orso82g5 only)
lattice semiconductor orca orso42g5 and orso82g5 data sheet 55 if core fifo cannot accept cells, cell_begin_ok will be low. if core fifo is empty then cell_begin_ok will be asserted every 4 clock cycles until cellvalid is asserted by user to indicate valid cell data. cellvalid: clock-wide pulse asserted by user to indicate valid data. asserted on the clock cycle following cell_begin_ok. figure 41. orso42g5 and orso82g5 transmit fpga interface opc2 cell mode when operating in the eight-link cell mode, the opc8 block passes user cells from fpga to embedded core. depending upon the con?ured cell size, cell transfers will take a variable number of sysclk156 cycles to be transmitted across the interface. data are always transferred across a 160-bit bus (20 octets per clock cycle). figure 42 shows ?e clock cycles for a cell transfer this corresponds to a user cell size of 91 octets. the two control signals in the ?ure are de?ed as: sdo_bp_8: backpressure signal from core instructing user to stop sending cell data. user should complete trans- mitting the current cell and can send one more cell before deasserting cellvalid. cellvalid: is high throughout a cell transfer to indicate valid cell data figure 42. orso82g5 transmit fpga interface opc8 cell mode sysclkx[1,2] cell_begin_ok_x[1,2] opc2_x[1,2][39:0] dddddd dd d ddddddd ddd dddd 1 cycle ? clk cycles cell siz e clk cycles (ocets) 75 79 83 91 16 16 20 20 opc2_x[1,2]_cellvalid sysclk156 8 sdo_bp_8 opc8[159:0] dddddd dd d ddddddd ddd dddd ? clk cycles cell siz e clk cycles (ocets) 75 79 83 91 4 4 5 5 opc8_cellvalid d ? clk cycles ? clk cycles
lattice semiconductor orca orso42g5 and orso82g5 data sheet 56 cell mode receive path the receive logic blocks unique to the cell mode are shown in figure 43 and are described in the next sections. prior to reaching this logic the received data has been demultiplexed, frame aligned and descrambled by the ser- des and sonet logic and is formatted on a per channel basis as 32-bit words with an accompanying clock. the clock is a 77.76 mhz clock provided by the demux block performing a divide-by-4 operation on rwckxx. the data extractor and receive fifo (rxfifo) process the data on a per channel basis. the receive fifo also performs a clock domain transfer to the 156 mhz domain of the input port controller (ipc2/8) blocks. the ipc2/8 blocks perform the two-link or eight-link (orso82g5 only) alignment functions. in two-link alignment mode, the received data are passed to the fpga logic as 40-bit words at the 156 mhz rate. in eight-link alignment mode, the received data are passed to the fpga logic as a single 160-bit word, again at the 156 mhz rate. additional mode- dependent status information is also provided across the core/fpga interface. figure 43. receive path logic unique to cell mode cell extractor this block is used only in cell mode and does the following: extracts user cells from the spe performs bip calculation/checks to verify cell integrity link header sequence interrogation processing options include: cell handling for invalid sequence (drop or pass to fpga) s/w con?urable ?ink removal due to excessive sequence errors data from the cell extractor block(s) is sent to the receive fifo which aligns the data to the system clock domain and provides for deskew between the links. cell extraction and bip calculation/checking the data from the descrambler are passed into the data extractor which strips the cell data from the payload of a sonet frame. the block extracts the bip value from the data stream and also perform an internal cell bip calcula- tion. if the bip value is not correct, an error ?g bit will set in the status registers. the block also determines when the next link header is coming in the frame and what the cell sequence number contained within it should be. if the value of the cell sequence counter is not equal to the expected value, an error ?g bit will set in the status registers and an error signal will be sent across the core/fpga interface. rx fifo data from other channel cell extractor rx fifo fifo write ipc2 control fifo read control or ipc8 block in two-link alignment group rx fifo data from other channels in eight-link alignment group ipc2_[a:b][1:2] or ipc8 sysclk156[a:b][1:2] or sysclk156 8 6 32 77.76 mhz
lattice semiconductor orca orso42g5 and orso82g5 data sheet 57 link header detector the link header detector determines when the next link header is coming in the frame and what the sequence number contained within it should be. if the value of the cell sequence counter is not equal to the expected value, then an error ?g bit will set in the status registers and an error signal will be sent to the fpga logic. the sequence counter will increment to the next sequence number. the sequence count value is not updated with the incorrect value, but is incremented each time a link header is received. if excessive sequence errors are detected (three or more in a row), and the auto_remove_[a:b] register bit is set, then the corresponding link will be treated as not valid. the rx_link_good status bit will go low indicating the link is no longer receiving cells. if the auto_remove_[a:b] register bit is not set, then the link is still valid when excessive sequence errors are detected. an oof condition will also trigger the link to be removed from ser- vice if the auto_remove_[a:b] register bit is set. at startup or after a link has been removed from service (indicated by rx_link_good going low), a link can be rejoined into the group. this is performed via the per block rejoin_[a:b] register bit. when rejoining a link the rx fifo will begin receiving cells. to cleanly rejoin a link into a group there are two methods to insure the rx fifo begins loading correctly. the ?st method is to use the fast framing mode during the rejoin process. the can be done by setting the ffrm_en_xx for the links that need to be rejoined before setting the rejoin_[a:b] bit. the second method is to issue a block reset to clear the fifo once all links that have been selected to be rejoined are rejoined. this is done by ?st setting the rejoin_[a:b] bit. once the rx_link_good status bit is high for the selected channels the gswrst_[a:b] for the block should be set and cleared to reset the block. this method will disturb traf? on all links in the block during the gswrst_[a:b] reset time. once all of the links in a group are rejoined and the traf? is again ?wing the rejoin_[a:b] bit should be cleared. if this bit is not cleared, a link may drop out using the auto_remove mode and the channel may be rejoined incorrectly, causing errors on the entire group. receive fifo the main clock domain transfer for the data path is handled by the receive fifo. a 16 x 161 fifo is used in cell mode. the fifo is implemented as a dual-port memory which will support simultaneous reads and writes. the receive fifo block is written to at 77.76 mhz and read at 156 mhz. the receive fifo can allow for inter-link skew of about 800 ns (16 x 160 = 2560 bits, 400 ps per bit gives 1024 ns). the 160 lsbs in the memory are received data and the 161st bit indicates the start of a new cell. the fifo write control logic indicates to the ipc, the start of a new frame of data. this signal will only be active for the a1 word of a frame. once frame synchronization has occurred and the ipc has responded with a fifo enable signal, data will be writ- ten into the memory. only the payload (cells) is written to the fifo. the toh bytes are not written into the fifo. the cell octets immediately following the a1a2 bytes will be always written to the top of the fifo. once a full cell has been written to the memory, the write control logic will send a control signal to the ipc8 or ipc2 block which will start the process of reading data from the fifo. the ipc will read one whole cell at a time from each of the 8 fifo blocks, if con?ured for the eight-link cell mode (orso82g5 only) or from each of 2 fifo blocks if con?ured for the two-link cell mode. a fifo occupancy counter generates a rx_fifo_ovrun indication to the register interface if it detects a fifo over?w condition. the cell mode allows for alignment of all eight-links or alignment of two-links. thus there will be two ipc blocks for two pairs of channels per block. input port controllers the input port controllers (ipcs) are the block responsible for ?irecting traf? for the receive traf? ?w. the block diagrams for the 2-link and 8-link ipcs are shown in figure 44. they provide the following essential functions. determining when cell data can be read from the fifos of the individual links.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 58 insuring group bundles are properly aligned. scheduling reads from the rx fifos. cells are read one at a time from the con?ured links. parsing the cell data into payload data (along with selected header information). cells which have errors that make them unusable (such as bip or sequence number errors) are thrown away. this dropping of errored cells can be disabled through register bits cell_bip_inh_xx and cell_seq_inx_xx. figure 44. ipc2 and ipc8 block diagrams there are 5 ipc blocks in the embedded core. there is an ipc2 block for every channel pair: ipc2_a1 combines links from channels aa,ab (orso82g5 only) ipc2_a2 combines links from channels ac,ad ipc2_b1 combines links from channels ba,bb (orso82g5 only) ipc2_b2 combines links from channels bc,bd the ipc8 block combines cells from all eight aligned links and transmits them to the fpga logic (orso82g5 only). before an ipc can begin reading data from the rx fifos and assembling cells, it must ?st align all fifos in a port bundle. this is accomplished by handshaking signals between the framer and the ipc. the framer indicates to the ipc that framing has been acquired. the framer does not start ?ling the fifos, however, until the next a1/a2 sonet signal. rx fifo ipc2 block ipc2_[a:b][1:2][39:0] sysclk156[a:b][1:2] 32 77.76 mhz rx fifo 32 77.76 mhz rx fifo ipc8 ipc8[159:0] sysclk156 8 32 77.76 mhz rx fifo 32 77.76 mhz link 0 link 1 link 0 link 7 40 160 fpga logic block fpga logic cell extractor cell extractor cell extractor cell extractor (orso82g5 only)
lattice semiconductor orca orso42g5 and orso82g5 data sheet 59 the behavior of the ipc is dependent on the auto_bundle register bit. if auto_bundle is set, the group will continue to operate even if a link (or several links) of the group is not valid (rx_link_good is low). if auto_bundle is not set the entire group must be valid (rx_link_good is high) for the group to receive cells through the ipc. the ipc must determine when fifo reads may begin. before reading data from a fifo can begin, the fifo must have a full cell available to be read. this is condition is indicated by a signal from each fifo which is monitored by the ipc. the ipc then makes sure that the cells in a given port are received in the order that they are transmitted. ipc receive cell mode timing core/fpga this section contains timing diagrams for major interfaces of this block to the fpga logic when cells are to be transferred. figure 45 shows the cell twin-link mode timing. the number of clock cycles to transfer the cell data depends on the payload size selected. error indications for cell bip errors and cell drop are also shown. figure 45. ipc2 data flow when operating in cell mode, the ipc2 block passes user cells as well as control and status signals to the user. depending upon the con?ured cell size, cell transfers will take a variable number of sysclk156 cycles to be received across the interface. data are always transferred across a 40-bit bus (5 octets per clock cycle). figure 45 shows 16 clock cycles for a cell transfer. this corresponds to a user cell size of 79 octets. figure 46 shows cell octal alignment mode timing for the orso82g5. when operating in cell mode, the ipc8 block aligns all 8 channels of receive data on a frame basis. the ipc8 also passes user cells as well as control and status signals to the user. depending upon the con?ured cell size, cell transfers will take a variable num- ber of sysclk156 cycles to be received across the interface. data are always transferred across an 160-bit bus (20 octets per clock cycle). figure 46 shows 4 clock cycles for a cell transfer. this corresponds to a user cell size of 79 octets. sysclk156x[1,2] ipc2_a[1,2]cellstart d d d ddd dd d ddddddd d ddd dddd 4 clk cycles ? clk cycles 4 clk cycles cell bip error if a cell bip error occurs, the cell_bip_err signal re?cts the occurrence, as shown in the figure. for 2-link cell mode, the cell_bip_err signal is asserted during the last 4 clock cycles of the receive cell. 4 clk cycles d ipc2_a[1,2]_bip_err ipc2_a[1,2]_celldrop ipc2_x[1,2][39:0] bip error is associated with current cell cell drop is associated with the next cell (no t present) cell bip error if a cell error occurs within the asb and; 1. cell_bip_inh=0 ...do not drop bip errored cells (s/w selectable) 2. a bip error occurs the drop indicator will preceed the user cell that con- tains the bip error. all data will be passed w/o modi?a- tion.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 60 figure 46. orso82g5 receive fpga/embedded core interface ipc8 mode in the serdes-only mode the data are simply transferred as 32-bit wide words to and from the fpga logic. the next sections describe the signal de?itions for the tx and rx paths in the sonet, opc2 and opc8 modes. the signal names unique to an operating mode are preferred for design and are generally the ones used in the isplever design environment. the labels in the left most column are the hardware fpga interface names. the isplever software creates an hdl module with speci? names based on the mode selected for each channel. the pin mappings performed by isplever are shown in table 11 through table 14. the interface signals for the embedded ram are completely independent of these signals. the memory signals are described in a later section. signal description for tx path (fpga to serdes core) ?orso42g5 signals are divided across four channels with 40 signals per channel. txdxx[39:0] is the set of 40 signals for a channel xx. the data signals multiplexing scheme is similar to the one used for the rxd signals. however, the status signals multiplexing is different. please refer to table 11 for a detailed description of the txd multiplexing scheme. for all channels the txdxx[39:33] signals are not used. table 11 summarizes the signals at the fpga/core interface in the transmit direction. sysclk156x[1,2] ipc8_cellstart dddddd dd d ddddddd dddd dddd ? clk cycles 4 clk cycles cell bip error if a cell bip error occurs, the cell_bip_err signal re?cts the occurrence, as shown in the figure. d ipc8_cell_bip_err ipc8_celldr op ipc8_[159:0] bip error is associated with current cell cell drop is associated with the next cell (not present) cell bip error if a cell error occurs within the asb and; 1. cell_bip_inh=0 (do not drop bip errored cells) 2. a bip error occurs the drop indicator will preceed the user cell that con- tains the bip error. all data will be passed w/o modi?a- tion. 1 cycle idle
lattice semiconductor orca orso42g5 and orso82g5 data sheet 61 table 11. tx fpga/core interface signaling ?orso42g5 signal description for tx path (fpga to serdes core) ?orso82g5 signals are divided across 8 channels with 40 signals per channel. txdxx[39:0] is the set of 40 signals for a channel xx. the data signals multiplexing scheme is similar to the one used for the rxd signals. however, the status signals multiplexing is different. please refer to table 12 for the detailed description of the txd multiplexing scheme. for all channels the txdxx[39:33] signals are not used. table 12 summarizes the signals at the fpga/core interface in the transmit direction. txdac sonet mode opc2 a2 mode [39:33] 32 dinac_fp [31:21] dinac[31:21] 20 dinac[20] opc2_a2_cellvalid [19:0] dinac[19:0] opc2_a2[39:20] txdad sonet mode opc2 a2 mode [39:33] 32 dinad_fp [31:21] dinad[31:21] 20 dinad[20] [19:0] dinad[19:0] opc2_a2[19:0] table 12. tx fpga/core interface signaling ?orso82g5 txdaa sonet mode opc2 a1 mode opc8 mode [39:33] 32 dinaa_fp [31:21] dinaa[31:21] 20 dinaa[20] opc2_a1_cellvalid [19:0] dinaa[19:0] opc2_a1[39:20] opc8[159:140] txdab sonet mode opc2 a1 mode opc8 mode [39:33] 32 dinab_fp [31:20] dinab[31:20] [19:0] dinab[19:0]] opc2_a1[19:0]] opc8[139:120]] txdac sonet mode opc2 a2 mode opc8 mode [39:33] 32 dinac_fp [31:21] dinac[31:21] 20 dinac[20] opc2_a2_cellvalid [19:0] dinac[19:0] opc2_a2[39:20] opc8[119:100] txdad sonet mode opc2 a2 mode opc8 mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 62 signal description for rx path (serdes core to fpga) ?orso42g5 signals are divided across four channels with 40 signals per channel. rxdxx[39:0] is the set of 40 signals for a channel xx. all rx direction signals are outputs from the core. see figure 47 for clock transfers across the fpga/core interface. in sonet mode, rxdxx[31:0] carries 32 bit data from the alignment fifo of the respective channel. rxdxx[35:32] carries miscellaneous information such as oof, biperr, frame pulse (fp), and spe. in cell mode, data from each of the four 2-link ipc bundles are spread across all eight channels and are assigned to the 20 lsbs (rxdxx[19:0]) of each channel output. data from ipc2_a1 is distributed across rxdaa[19:0] and rxdab[19:0]. data from ipc2_a2 is distributed across rxdac[19:0] and rxdad[19:0]. this symmetry is maintained for ipc2 data signals from block b. the ipc status signals for cell mode operation are contained in rxdxx[39:36] and rxdxx[33]. the signals for sonet mode operation are assigned to rxdxx[35:34] and rxdxx[33]. [39:33] 32 dinad_fp [31:21] dinad[31:21] 20 dinad[20] opc8_cellvalid [19:0] dinad[19:0] opc2_a2[19:0] opc8[99:80] txdba sonet mode opc2 b1 mode opc8 mode [39:33] 32 dinba_fp [31:21] dinba[31:21] 20 dinba[20] opc2_b1_cellvalid [19:0] dinba[19;0]] opc2_b1[39:20] opc8[79:60] txdbb sonet mode opc2 b1 mode opc8 mode [39:33] 32 dinbb_fp [31:20] dinbb[31:20] [19:0] dinbb[19:0] opc2_b1[19:0] opc8[59:40] txdbc sonet mode opc2 b2 mode opc8 mode [39:33] 32 dinbc_fp [31:21] dinbc[31:21] 20 dinbc[20] opc2_b2_cellvalid [19:0] dinbc[19:0] opc2_b2[39:20] opc8[39:20] txdbd sonet mode opc2 b2 mode opc8 mode [39:33] 32 dinbd_fp [31:20] dinbd[31:20] [19:0] dinbd[19:0] opc2_b2[19:0] opc8[19:0] table 12. tx fpga/core interface signaling ?orso82g5 (continued)
lattice semiconductor orca orso42g5 and orso82g5 data sheet 63 note that rxdxx[39:32] signal assignments are the same no matter what mode the rx blocks are in. table 13 summarizes the signals across the core/fpga interface in the receive direction. table 13. rx core/fpga interface signals ?orso42g5 rxdac[39:0] sonet mode ipc2 a2 mode 39 sync2_a2_oos 38 ipc2_a2_celldrop 37 ipc2_a2_cellstart 36 doutac_fp 35 doutac_oof 34 doutac_spe 33 ipc2_a2_cell_bip_err 32 doutac_b1_err [31:20] doutac[31:20]] [19:0] doutac[19:0] ipc2_a2[39:20] rxdad[39:0] sonet mode ipc2 a2 mode 39 38 37 cell_begin_ok_a2 36 doutad_fp 35 doutad_oof 34 doutad_spe 33 32 doutad_b1_err [31:20] doutad[31:20] [19:0] doutad[19:0] ipc2_a2[19:0] rxdbc[39:0] sonet mode ipc2 b2 mode 39 sync2_b2_oos 38 ipc2_b2_celldrop 37 ipc2_b2_cellstart 36 doutbc_fp 35 doutbc_oof 34 doutbc_spe 33 ipc2_b2_cell_bip_err 32 doutbc_b1_err [31:20] doutbc[31:20] [19:0] doutbc[19:0] ipc2_b2[39:20] rxdbd[39:0] sonet mode ipc2 b2 mode 39 38 sync4_b_oos 37 cell_begin_ok_b2 36 doutbd_fp 35 doutbd_oof 34 doutbd_spe
lattice semiconductor orca orso42g5 and orso82g5 data sheet 64 signal description for rx path (serdes core to fpga) ?orso82g5 signals are divided across 8 channels with 40 signals per channel. rxdxx[39:0] is the set of 40 signals for a channel xx. all rx direction signals are outputs from the core. see figure 47 for clock transfers across the fpga/core interface. in sonet mode, rxdxx[31:0] carries 32 bit data from the alignment fifo of the respective channel. rxdxx[35:32] carries miscellaneous information such as oof, biperr, frame pulse (fp), and spe. in cell mode, data from each of the four 2-link ipc bundles are spread across all eight channels and are assigned to the 20 lsbs (rxdxx[19:0]) of each channel output. data from ipc2_a1 is distributed across rxdaa[19:0] and rxdab[19:0]. data from ipc2_a2 is distributed across rxdac[19:0] and rxdad[19:0]. this symmetry is maintained for ipc2 data signals from block b. data from the 8-link ipc block ipc8 is spread across all eight channels and assigned to the 20 lsbs (rxdxx[19:0] of each channel output. the ipc status signals for cell mode operation are contained in rxdxx[39:36] and rxdxx[33]. the signals for sonet mode operation are assigned to rxdxx[35:34] and rxdxx[33]. note that rxdxx[39:32] signal assignments are the same no matter what mode the rx blocks are in. table 14 summarizes the signals across the core/fpga interface in the receive direction. 33 32 doutbd_b1_err [31:20] doutbd[31:20] [19:0] doutbd[19:0] ipc2_b2[19:0] table 14. rx core/fpga interface signals ?orso82g5 rxdaa[39:0] sonet mode ipc2 a1 mode ipc8 mode 39 sync2_a1_oos 38 ipc2_a1_celldrop 37 ipc2_a1_cellstart 36 doutaa_fp 35 doutaa_oof 34 doutaa_spe 33 ipc2_a1_cell_bip_err 32 doutaa_b1_err [31:20] doutaa[31:20] [19:0] doutaa[19:0] ipc2_a1[39:20] rxdab[39:0] sonet mode ipc2 a1 mode ipc8 mode 39 38 sync4_a_oos 37 cell_begin_ok_a1 36 doutab_fp 35 doutab_oof 34 doutab_spe table 13. rx core/fpga interface signals ?orso42g5 (continued)
lattice semiconductor orca orso42g5 and orso82g5 data sheet 65 33 32 doutab_b1_err [31:20] doutab[31:20]] [19:0] doutab[19:0] ipc2_a1[19:0] ipc8[139:120] rxdac[39:0] sonet mode ipc2 a2 mode ipc8 mode 39 sync2_a2_oos 38 ipc2_a2_celldrop 37 ipc2_a2_cellstart 36 doutac_fp 35 doutac_oof 34 doutac_spe 33 ipc2_a2_cell_bip_err 32 doutac_b1_err [31:20] doutac[31:20]] [19:0] doutac[19:0] ipc2_a2[39:20] ipc8[119:100] rxdad[39:0] sonet mode ipc2 a2 mode ipc8 mode 39 ipc8_celldrop 38 ipc8_cellstart 37 cell_begin_ok_a2 36 doutad_fp 35 doutad_oof 34 doutad_spe rxdad[39:0] sonet mode ipc2 a2 mode ipc8 mode 33 ipc8_cell_bip_err 32 doutad_b1_err [31:20] doutad[31:20] [19:0] doutad[19:0] ipc2_a2[19:0] ipc8[99:80] rxdba[39:0] sonet mode ipc2 b1 mode ipc8 mode 39 sync2_b1_oos 38 ipc2_b1_celldrop 37 ipc2_b1_cellstart 36 doutba_fp 35 doutba_oof 34 doutba_spe 33 ipc2_b1_cell_bip_err 32 doutba_b1_err [31:20] doutba[31:20] [19:0] doutba[19:0] ipc2_b1[39:20] ipc8[79:60] rxdbb[39:0] sonet mode ipc2 b1 mode ipc8 mode 39 sync8_oos 38 sdo_bp_8 table 14. rx core/fpga interface signals ?orso82g5 (continued)
lattice semiconductor orca orso42g5 and orso82g5 data sheet 66 37 cell_begin_ok_b1 36 doutbb_fp 35 doutbb_oof 34 doutbb_spe 33 32 doutbb_b1_err [31:20] doutbb[31:20] [19:0] doutbb[19:0] ipc2_b1[19:0] ipc8[59:40] rxdbc[39:0] sonet mode ipc2 b2 mode ipc8 mode 39 sync2_b2_oos 38 ipc2_b2_celldrop 37 ipc2_b2_cellstart 36 doutbc_fp 35 doutbc_oof 34 doutbc_spe 33 ipc2_b2_cell_bip_err 32 doutbc_b1_err [31:20] doutbc[31:20] [19:0] doutbc[19:0] ipc2_b2[39:20] ipc8[39:20] rxdbd[39:0] sonet mode ipc2 b2 mode ipc8 mode 39 38 sync4_b_oos 37 cell_begin_ok_b2 36 doutbd_fp 35 doutbd_oof 34 doutbd_spe 33 32 doutbd_b1_err [31:20] doutbd[31:20] [19:0] doutbd[19:0] ipc2_b2[19:0] ipc8[19:0] table 14. rx core/fpga interface signals ?orso82g5 (continued)
lattice semiconductor orca orso42g5 and orso82g5 data sheet 67 reference clock requirements there are two pairs of reference clock inputs in the orso42g5 and orso82g5 devices. each reference clock is distributed to all channels in a block. each channel has a differential buffer to isolate the clock from the other chan- nels. the input clock is preferably a differential signal; however, the device can operate with a single-ended input. the input reference clock directly impacts the transmit data eye, so the clock should have low jitter. in particular, jit- ter components in the dc to 5 mhz range should be minimized. the required electrical characteristics for the refer- ence clock are given in table 46. synthesized and recovered clocks the serdes embedded core block contains its own dedicated plls for transmit and receive clock generation. the user provides a reference clock of the appropriate frequency, as described in the previous section. the trans- mitter pll uses the refclk_[a,b] inputs to synthesize the internal high-speed serial bit clocks. the receiver plls extract the clock from the serial input data and retime the data with the recovered clock. the receive pll for each channel has two modes of operation - lock to reference and lock to data with retiming. when no data or invalid data is present on the hdinp_xx and hdinn_xx pins, the receive vco will not lock to data and its frequency can drift outside of the nominal ?00 ppm range. under this condition, the receive pll will lock to refclk_[a,b] for a ?ed time interval and then will attempt to lock to receive data. the process of attempting to lock to data, then locking to clock will repeat until valid input data exists. there is also a control register bit per channel to force the receive pll to always lock to the reference clock. the high-speed transmit and receive serial data links can run at 0.6 to 2.7 gbits/s, depending on the frequency of the reference clock and the state of the control bits from the internal transmit control register. the interface to the serializer/deserializer block runs at 1/8th the bit rate of the data lane. additionally, the mux/demux logic converts the data rate and bit-width so the fpga core can run at 1/4th this frequency which gives a range of 18.8 to 84.4 mhz for the data in and out of the fpga in sonet mode. in cell mode, there is a clock domain transfer to a 2x clock domain, which gives a range of 37.5 to 168.8 mhz for the data in and out of the fpga. internal clock signals at the fpga/core interface there are several clock signals de?ed at the fpga/embedded core interface in addition to the external reference clock for each serdes block. all of the orso42g5 and orso82g5 clock signals are shown in figure 47 and are described following the ?ure.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 68 figure 47. orso42g5 and orso82g5 clock signals, block a (high speed serial i/o also shown. block b has the same signals, sysclk156 8 is unique to the orso82g5 and common to both blocks). refclkp_[a:b], refclkn_[a:b] : these are the differential reference clocks provided to the orso42g5 and orso82g5 device as described earlier. they are used as the reference clock for both tx and rx paths. for oper- ation of the serial links at 2.48 gbits/s, the reference clocks will be at a frequency of 155.52 mhz. rwck[aa:bd] : these are the low-speed receive clocks from the embedded core to the fpga across the core- fpga interface. these are derived from the recovered low-speed complementary clocks from the serdes blocks. rwckaa belongs to channel aa, rwckab belongs to channel ab and so on. with a reference clock input of 155.52 mhz, these clocks operate at 77.76 mhz. rck78[a:b] : these are muxed outputs of rwcka[a:d] and rwckb[b:d] respectively. with a reference clock input of 155.52 mhz, these clocks operate at 77.76 mhz. rsysclk[a:b][1:2] : these clocks are inputs to the serdes block a and b respectively from the fpga. these are used by each channel as the read clock to read received data from the alignment fifo within the embedded core. clocks rsysclka[1:2] are used by channels in the serdes block a and rsysclkb[1:2] by channels in the serdes block b. to guarantee that there is no over?w in the alignment fifo, it is an absolute requirement that the write and read clocks be frequency locked within 0 ppm. examples of how to achieve this are shown in the later section on recommended board-level clocking. fpga logi c common logic, channel aa (orso82g5 only) channel ab (orso82g5 only) channel ad channel ac rck78a tck78a rsys_clk_a1 tsys_clk_aa rw ckaa rw ckab tsys_clk_ab rwckac tsys_clk_ac rsys_clk_a2 tsys_clk_ad rwckad refclk[p:n]_a 2 hdin[p:n]_ac 2 hdout[p:n]_ad hdin[p:n]_ad 2 hdout[p:n]_a c hdout[p:n]_ab 2 hdin[p:n]_ab 2 hdout[p:n]_aa 2 hdin[p:n]_aa 2 2 2 serial links cell mode all modes sonet mode tck156a tck39a tsysclk156 a1 sysclk156 8 (orso82g5 only) tsysclk156 a2 block a rwckac
lattice semiconductor orca orso42g5 and orso82g5 data sheet 69 tck156[a:b] : this is a muxed output from the core to the fpga across the core-fpga interface of one of the 4 transmit serdes clocks per block. there is one clock output per serdes block. it is derived from refclk_[a:b] and runs at the reference clock frequency.this clock is available from the core in all modes and used by the core in cell mode. tck78[a:b] : this is a muxed output from the core to the fpga across the core-fpga interface of one of the 4 transmit serdes clocks per block. there is one clock output per serdes block. it is derived from refclk_[a:b] and runs at half the reference clock frequency. this clock is available from the core in all modes and used by the core in sonet and serdes-only mode. tck39[a:b] : this is a muxed output from the core to the fpga across the core-fpga interface of one of the 4 transmit serdes clocks per block. there is one clock output per serdes block. it is derived from refclk_[a:b] and runs at a quarter of the reference clock frequency. this clock is available from the core in all modes. tsysclk[aa,?d] : these clocks are inputs to the serdes block a and b respectively from the fpga. these are used by each channel to control the timing of the transmit data path in the sonet and serdes-only modes. (they are not used in cell mode.) to guarantee correct transmit operation theses clocks must be frequency locked within 0 ppm to tck78[a:b]. sysclk156 [a:b][1:2] and sysclk156 8 : these clocks are inputs to the serdes block a and b from the fpga. and are used by the cell processing blocks within the embedded core. clocks sysclk156 a[1:2] are used by channels in the serdes block a and sysclk156 b[1:2] by channels in the serdes block b for two-link cell mode operation. sysclk156 8 is used by both blocks for eight-link cell mode in the orso82g5. sample initialization sequences ?orso42g5 the following paragraphs show sample control register write sequences for initialization and resynchronization for the major modes of the device. hexadecimal values will be shown for the data to be written into the control regis- ters. for these values bit 0 will be the msb while bit 7 is the lsb. for the per-channel control registers, only the ?st register address is shown. the other per-channel control registers must also be initialized for the desired mode. 1. serdes-only mode initialization ?orso42g5 set serdes only mode (per channel, channel aa selected for sample initialization) 30823 and 30833 40 set serdes pll to lock to data signal (per channel, channel aa selected for sample initialization) 30824 and 30834 80 toggle soft_reset once all clocks have stabilized 30a06 01 30a06 00 provide a rising edge on the dinxx_start signal 2. sonet mode initialization ?orso42g5 this sample initialization uses the alignment fifo for two channel alignment and auto_soh mode set dual channel alignment (per channel, channels ac and ad) 30822 and 30833 10 set serdes pll to lock to data signal (per channel, channels ac and ad) 30824 and 30834 80 set auto_soh mode (per channel, channels ac and ad) 30826 and 30836 03
lattice semiconductor orca orso42g5 and orso82g5 data sheet 70 toggle soft_reset once all clocks have stabilized 30a06 01 30a06 00 3. sonet alignment fifo resynchronization ?orso42g5 if during operation a link goes oof the alignment group will continue to run without the errored channel. to realign this link with the rest of group once the oof condition is cleared the group may need to be resynchronized. this operation (for 4 channel alignment in block a) is shown below. toggle the fmpu_resync2_a2 register bit to reset the alignment fifo group. 30a04 04 30a04 00 this sequence will stop traf? temporarily on all links in the alignment grouping. 4. two-link cell mode initialization ?orso42g5 this sample initialization uses 2-link cell mode on all links (a1, a2, b1, and b2). auto_bundle and auto_remove are both used for these links. the gswrst_[a:b] rejoin method is used. set serdes pll to lock to data signal and auto_toh mode (per channel, all channels) 30824 and 30834 82 enable auto_remove and rejoin 30a03 1b set 2-link cell mode for groups a2 and b2 30a05 0a toggle soft_reset 30a06 01 30a06 00 set the tx_cfg_done bit to indicate the transmitter is completely con?ured 30a07 01 toggle gswrst_[a:b] to clear the rx fifos 30005 20 30105 20 30005 00 30105 00 turn off rejoin (clear the rejoin register bits) and enable auto_bundle 30a03 49 sample initialization sequences ?orso82g5 the following paragraphs show sample control register write sequences for initialization and resynchronization for the major modes of the device. hexadecimal values will be shown for the data to be written into the control regis- ters. for these values bit 0 will be the msb while bit 7 is the lsb. for the per-channel control registers, only the ?st register address is shown. the other per-channel control registers must also be initialized for the desired mode. 1. serdes-only mode initialization ?orso82g5 set serdes only mode (per channel, channel aa selected for sample initialization) 30803 40 set serdes pll to lock to data signal (per channel, channel aa selected for sample initialization) 30804 80
lattice semiconductor orca orso42g5 and orso82g5 data sheet 71 toggle soft_reset once all clocks have stabilized 30a06 01 30a06 00 provide a rising edge on the dixxx_start signal 2. sonet mode initialization ?orso82g5 this sample initialization uses the alignment fifo for 4 channel alignment and auto_soh mode set 4 channel alignment (per channel, all channels in block a) 30802, etc. 60 set serdes pll to lock to data signal (per channel, all channels in block a) 30804, etc. 80 set auto_soh mode (per channel, all channels in block a) 30806, etc. 03 set no_tx_rdi_exseq global register (block a). this is required to stop cell mode blocks from sending rdi due to no cells. 30a03 80 toggle soft_reset once all clocks have stabilized 30a06 01 30a06 00 3. sonet alignment fifo resynchronization ?orso82g5 if during operation a link goes oof the alignment group will continue to run without the errored channel. to realign this link with the rest of group once the oof condition is cleared the group may need to be resynchronized. this operation (for 4 channel alignment in block a) is shown below. toggle the fmpu_resync4_4 register bit to reset the alignment fifo group. 30a04 48 30a04 00 this sequence will stop traf? temporarily on all links in the alignment grouping. 4. two-link cell mode initialization ?orso82g5 this sample initialization uses 2-link cell mode on all links (a1, a2, b1, and b2). auto_bundle and auto_remove are both used for these links. the gswrst_[a:b] rejoin method is used. set serdes pll to lock to data signal and auto_toh mode (per channel, all channels) 30804, etc. 82 set auto_remove and rejoin 30a03 1b set 2-link cell mode for all groups a1, a2, b1 and b2 30a05 1e toggle soft_reset 30a06 01 30a06 00 set the tx_cfg_done bit to indicate the transmitter is completely con?ured 30a07 01
lattice semiconductor orca orso42g5 and orso82g5 data sheet 72 toggle gswrst_[a:b] to clear the rx fifos 30005 20 30105 20 30005 00 30105 00 clear the rejoin register bits and set auto_bundle 30a03 49 5. eight-link cell mode initialization ?orso82g5 this sample initialization uses 8-link cell mode. auto_bundle and auto_remove are both used for these links. the gswrst_[a:b] rejoin method is used. set serdes pll to lock to data signal and auto_toh mode (per channel, all channels) 30804, etc. 82 set auto_remove, and rejoin 30a03 1b set 8-link cell mode 30a05 01 toggle soft_reset 30a06 01 30a06 00 set the tx_cfg_done bit to indicate the transmitter is completely con?ured 30a07 01 toggle gswrst_[a:b] to clear the rx fifos 30005 20 30105 20 30005 00 30105 00 once all of the rx_link_goods are high, clear the rejoin register bits and set auto_bundle 30a03 49 reset conditions the serdes block can be reset in one of three different ways: on power up, using the hardware reset (pasb_resetn) or by setting bits in the control registers. the power up reset process begins when the power supply voltage ramps up to approximately 80% of the nominal value of 1.5v. following this event, the device will be ready for normal operation after 3 ms. a hardware reset is initiated by making the pasb_resetn low for at least two microprocessor clock cycles. the device will be ready for operation 3 ms after the low to high transition of the pasb_resetn. this reset function affects all serdes blocks and resets all core control, status and data path registers and counters. using the software reset option, each channel can be individually reset by setting swrst bit to a logic 1 in the serdes channel con?uration register. the device will be ready 3 ms after the swrst bit is deasserted. simi- larly, all four channels per block serdes can be reset by setting the global reset bit gswrst. the device will be ready for normal operation 3 ms after the gswrst bit is deasserted. note that the software reset options resets only the serdes internal registers and counters on a per channel or per block basis. the core non-seres regis- ters and logic blocks are not affected. it should also be noted that the embedded core registers and logic blocks cannot be accessed until after fpga con?uration is complete.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 73 table 15 summarizes the conditions under which the embedded core registers, serdes, and embedded core logic are reset under user control. the embedded core status registers are also reset on read. table 15. orso42g5 and orso82g5 embedded core reset conditions serdes characterization test mode (orso82g5 only) the serdes characterization mode is a test mode that allows for direct control and observation of the transmit and receive serdes interfaces at chip ports. with these modes the serdes logic and i/o can be tested one channel at a time in either the receive or transmit modes. the serdes characterization mode is available for only one block (block b) of the orso82g5. the characterization test mode is con?ured by setting bits in the control registers via the system bus. there are four bits that set up the test mode. the transmit characterization test mode is entered when schar_ena=1 and schar_txsel=1. entering this mode will cause chip port inputs to directly control the serdes low-speed trans- mit ports of one of the channels as shown in table 16. table 16. serdes transmit characterization mode the x in the table will be a single channel in serdes quad b, selected by the schar_chan control bits. the decoding of schar_chan is shown in table 17. reset signal data paths control and status registers tck156[a:b] tck78[a:b] tck39[a:b] rck78[a:b] rwckxx notes power up reset reset reset reset power on reset pasb_resetn pin = 0 (hard reset) reset reset reset reset external input pin fpga con?uration reset reset reset reset done pin = 0 partial fpga recon?uration (with option disable tri_io) done pin = 0 internal signal fpga_reset = 1 reset fpga_reset is fpga sourced fpga gsrn signal = 0 optional optional gsrn is fpga sourced. set gsrn_disable = 1 to disable this reset soft_reset = 0, 1, 0 (system bus register based) reset reset write soft_reset = 1 (on) then write soft_reset = 0 (off) ts_all pin = 1 external input pin swrst_xx= 0,1,0 xx = [ac, ad, ba, bd] or [aa,...,bd] selected channel reset selected channel reset selected channel reset per channel software reset (not self-clearing, must be manually set and cleared.) gswrst_[a:b] = 0,1,0 selected block reset selected block reset selected block reset per block software reset (not self-clearing, must be manually set and cleared.) chip port serdes input pschar_ckio0 tbcbx pschar_ldio[9:0] ldinbx[9:0]
lattice semiconductor orca orso42g5 and orso82g5 data sheet 74 table 17. decoding of schar_chan the receive characterization test mode is entered when schar_ena=1 and schar_txsel=0, in this mode, one of the channels of serdes outputs is observed at chip ports as shown in table 18. the channel that is observed is also based on the decoding of schar_chan as shown in table 18. table 18. serdes receive characterization mode embedded core block ram there are two independent memory slices (labeled a and b) in the embedded core. each memory slice has a capacity of 4k words by 36 bits. these are in addition to the block rams found in the fpga portion of the orso42g5 and orso82g5. although the memory slices are in the embedded core part of the chip, they do not interact with the rest of the embedded core circuits, but are standalone memories designed speci?ally to increase ram capacity in the orso42g5 and orso82g5 chip. they can be used by the soft ip cores implemented in the fpga portion of the fpsc. a block diagram of a memory slice is shown in figure 48. each memory slice is organized into two sections (labeled sram a and sram b) and has one read port, one write port and four byte-write-enable (active-low) sig- nals. each byte has eight data bits and a control/parity bit. the control/parity bit responds to the same byte enable (bytewn_x[x]) as its corresponding data. no special logic such as parity checking is performed on this bit by the core. the read data from the memory is registered so that it works as a pipelined synchronous memory block. the minimum timing speci?ations are shown in figure 49 and figure 50. signal names and functions are summarized later in table 19 and follow the general series 4 naming conventions. schar_chan0 schar_chan1 channel 0 0 ba 1 0 bb 0 1 bc 1 1 bd serdes output chip port ldoutbx[9:0] pschar_ldio[9:0] rbc0bx pschar_ckio0 rbc1bx pschar_ckio1
lattice semiconductor orca orso42g5 and orso82g5 data sheet 75 figure 48. block diagram, embedded core memory slice figure 49. minimum timing specs for memory blocks-write cycle (-1 speed grade) 4k x 36 d_x[35:0] memory slice (1 of 2) 2k x 36 memory 2k x 36 memory (sram a) (sram b) write ports ckw_x cswa_x cswb_x aw_x[10:0] bytewn_x[3] bw[35,31:24] bytewn_x[2] bw[34,23:16] bytewn_x[1] bw[33,15:8] bytewn_x[0] bw[32,7:0] q_x[35:0] ckr_x csr_x ar_x[10:0] read ports side a / write selects side b fpga logic ram block read selects 36 11 36 11 note: x=[a,b] slice identifier parity data csw[a,b] aw[10:0] ckw d[35:0] bytewn[3:0] 1.5 ns 2.0 ns 0.5 ns 0.3 ns 0.5 ns 0.3 ns 0.5 ns 0.3 ns 0.7 ns 0.3 ns
lattice semiconductor orca orso42g5 and orso82g5 data sheet 76 figure 50. minimum timing specs for memory blocks-read cycle (-1 speed grade) table 19 summarizes the embedded memory signals at the core/fpga interface. in the table, an input refers to a signal ?wing into the embedded core and an output refers to a signal ?wing out of the embedded core. table 19. embedded memory core/fpga interface signal description register maps the memory map for the orso42g5 and orso82g5 core is only part of the full memory map of the orso42g5 and orso82g5 devices. the orso42g5 and orso82g5 are orca series 4 based devices and thus use the system bus as a communication bridge. the orso42g5 and orso82g5 core register map contained in this data sheet only covers the embedded asic core of the device, not the entire device. the system bus itself, and the generic fpga memory map, are fully documented in the mpi/system bus application note. as part of the system bus, the embedded asic core of an fpsc is located at address offset 0x30000. the orso42g5 and orso82g5 embedded core is an eight-bit slave interface on the series 4 system bus. the orso42g5 and orso82g5 core registers are clocked by the system bus main clock. each orca device contains a device id. this device id is unique to each orca device and can be used for device identi?ation and assist in the system debugging. the device id is located at absolute address 0x0-0x3. the orso42g5 and orca82g5 device ids are 0xdc012282. more information on the device id and other series 4 generic registers can be found in technical note tn1017, orca series 4 mpi/system bus. if a clock is not provided to the reference clock, the registers will fail to operate. fpga/embedded core interface signal name] input (i) to or output (o) from core signal description memory slice interface signals d_[a:b][35:0] i data in ?memory slice [a:b] ckw_[a:b] i write clock ?memory slice [a:b]. cswa_[a:b] i write chip select for sram a ?memory slice [a:b]. cswb_[a:b] i write chip select for sram b ?memory slice [a:b]. aw_[a:b][10:0] i write address ?memory slice [a:b]. bytewn_[a:b][3:0] i write control pins for byte-at-a-time write-memory slice [a:b]. q_[a:b][35:0] o data out ?memory slice [a:b]. ckr_[a:b] i read clock ?memory slice [a:b]. csr_[a:b] i read chip select ?memory slice [a:b]. csr_[a:b]= 0 selects sram a. csr_[a:b]= 1 selects sram b. ar_[a:b][10:0] i read address ?memory slice [a:b]. ckr ar[10:0], csr q[35:0] 1.5 ns 1.5 ns 4.5 ns 0.5 ns 2.0 ns 0 ns
lattice semiconductor orca orso42g5 and orso82g5 data sheet 77 the orso42g5 and orso82g5 core registers do not check for parity on a write operation. on a read operation, no parity is generated, and a ? is passed back to the initiating bus master interface on the parity signal line. types of registers the registers in orso42g5 and orso82g5 are 8-bit memory locations which, in general, can be classi?d into several types: general core status registers read-only registers to convey the status information of various operations within the fpsc core. an example is the state of the lki-xx receive pll lock indicator outside the serdes. alarm status and mask registers the alarm status registers are enabled or masked by the corresponding alarm enable registers. an example of such an alarm is the out-of-frame (oof) bit oof_xx which is enabled by the corresponding alarm enable bit oof_enxx (xx indicates one of the serdes channels). (the oof and bip error alarms are also available as sig- nals across the core-fpga boundary for each channel.) all the alarms for a given channel will be read into a single status bit (alarm_status_[aa-bd]). in addition, an event on any of these alarm status bits will generate an inter- rupt to the fpsc slave of the interrupt cause register on the system bus interface (see technical note tn1017). all alarm and status registers are clear on read. control registers read-write registers to setup the control inputs that de?e the operation of the fpsc core. the serdes block within the orso42g5 and orso82g5 core has a set of status and control registers for its operation. there is another group of status and control registers which are implemented outside the serdes, which are related to the serdes and other functional blocks in the fpsc core. they will be described in detail here. each serdes has four independent channels, which are named a, b, c or d. using this nomenclature, the ser- des a channels are named as aa, ab, ac and ad, while serdes b channels will be ba, bb,bc and bd. the register address allocation for the orso82g5 is shown in table 20. detailed descriptions of all of the register bits are provided in table 21 through table 36. table 20. memory space allocation in the fpsc core address (hex) description 3000x channel a in serdes a block, internal registers (not available in the orso42g5) 3001x channel b in serdes a block, internal registers (not available in the orso42g5) 3002x channel c in serdes a block, internal registers 3003x channel d in serdes a block, internal registers 3010x channel a in serdes b block, internal registers (not available in the orso42g5) 3011x channel b in serdes b block, internal registers (not available in the orso42g5) 3012x channel c in serdes b block, internal registers 3013x channel d in serdes b block, internal registers 3080x channel aa registers outside the serdes (not available in the orso42g5) 3081x channel ab registers outside the serdes (not available in the orso42g5) 3082x channel ac registers outside the serdes 3083x channel ad registers outside the serdes 3090x channel ba registers outside the serdes (not available in the orso42g5) 3091x channel bb registers outside the serdes (not available in the orso42g5) 3092x channel bc registers outside the serdes 3093x channel bd registers outside the serdes 30axx all channels registers
lattice semiconductor orca orso42g5 and orso82g5 data sheet 78 register reset conditions the reset conditions for the registers vary depending on register type. see the tables and the accompanying text for a description of the reset conditions. table 21. serdes alarm and alarm mask register descriptions ?orso42g5 (0x) absolute address bit name reset value (0x) description mode serdes alarm registers (read only) xx = [ac, ad, bc, bd] 30020 - ac 30030 - ad 30120 - bc 30130 - bd [0] rsvd 00 reserved - may be non-zero [1] lki_xx receive pll lock indication, channel xx. lki_xx = 1 indicates the receive pll is locked. note that the pll can either lock to the incom- ing data or to reclk_[a:b]. if the pll is locked to data and the data stream is terminated, lki_xx will go low until the pll locks to refclk_[a:b]. both [2:7] rsvd reserved - may be non-zero serdes alarm mask registers (read/write) xx = [ac, ad, bc, bd] 30021 - ac 30031 - ad 30121 - bc 30131 - bd [0] rsvd ff reserved [1] mlki_xx mask receive pll lock indication, channel mlki_xx = 1 indicates lki_xx is enabled both [2:7] rsvd reserved
lattice semiconductor orca orso42g5 and orso82g5 data sheet 79 table 22. serdes per-channel transmit con?uration register descriptions ?orso42g5 table 23. serdes per-channel receive con?uration register descriptions ?orso42g5 (0x) absolute address bit name reset value (0x) description mode serdes transmit per-channel con?uration registers (read/write) xx = [ac, ad, bc, bd] 30022 - ac 30032 - ad 30122 - bc 30132 - bd [0] txhr_xx 00 transmit half rate selection bit, channel xx. when txhr_xx = 1, hdout_xx's baud rate = (refclk[a:b]*8) and tck78[a:b] =(ref- clk[a:b]/4); when txhr_xx=0, hdout_xx's baud rate = (refclk[a:b]*16) and tck78[a:b]=(refclk[a:b]/2). txhr_xx = 0 on device reset. both [1] pwrdnt_xx transmit powerdown control bit, channel xx. when pwrdnt_xx = 1, sections of the trans- mit hardware are powered down. pwrdnt_xx = 0 on device reset. both [2] pe0_xx transmit preemphasis selection bit 0, channel xx. pe0_xx and pe1_xx select one of three pre- emphasis settings for the transmit section. peo_xx=pe1_xx = 0, preemphasis is 0%; peo_xx=1, pe1_xx = 0 or peo_xx=0, pe1_xx = 1, preemphasis is 12.5%; peo_xx=pe1_xx = 1, preemphasis is 25%. peo_xx=pe1_xx = 0 on device reset. both [3] pe1_xx both [4] hamp_xx transmit half amplitude selection bit, channel xx. when hamp_xx = 1, the transmit output buffer voltage swing is limited to half its normal amplitude. otherwise, the transmit output buffer maintains its full voltage swing. hamp_xx = 0 on device reset. both [5:7] rsvd reserved, always set to ?00 (0x) absolute address bit name reset value (0x) description mode serdes receive per-channel con?uration registers (read/write) xx = [ac, ad, bc, bd] 30023 - ac 30033 - ad 30122 - bc 30132 - bd [0] rxhr_xx 20 receive half rate selection bit, channel xx. when rxhr_xx =1, hdin_xx's baud rate = (refclk[a:b]*8) and rck78[a:b]=(ref- clk[a:b]/4); when rxhr_xx=0, hdin_xx's baud rate = (refclk[a:b]*16) and rck78[a:b]=(refclk/2). rxhr_xx = 0 on device reset. both [1] pwrdnr_xx receiver power down control bit, channel xx. when pwrdnr_xx = 1, sections of the receive hardware are powered down. pwrdnr_xx = 0 on device reset. both [2:7] rsvd reserved (bit 2 = 1 on device reset)
lattice semiconductor orca orso42g5 and orso82g5 data sheet 80 table 24. serdes per channel con?uration registers (read/write) ?orso42g5 (0x) absolute address bit name reset value (0x) description mode serdes per channel transmit and receive channel con?uration registers (read/write) xx = [ac, ad, bc, bd] 30024 - ac 30034 - ad 30124 - bc 30134 - bd [0] rsvd 40 reserved [1] mask_xx transmit and receive alarm mask bit, channel xx. when mask_xx = 1, the transmit and receive alarms of a channel are prevented from generating an alarm (i.e., they are masked or disabled). the mask_xx bit overrides the indi- vidual alarm mask bits in the alarm mask reg- isters. mask_xx = 1 on device reset. both [2] swrst_xx transmit and receive software reset bit, channel xx. when swrst_xx = 1, this bit pro- vides the same function as the hardware reset, except that all con?uration register settings are unaltered. this is not a self-clearing bit. once set, this bit must be manually set and cleared. swrst = 0 on device reset. both [3:6] rsvd reserved [7] testen_xx transmit and receive test enable bit, channel xx. when testen_xx = 1, the transmit and receive sections of channel xx are place in test mode. the testmode_xx bits (30006, 30106, etc.) must be set to specify the desired test. the gtesten_[a:b] bits override the individual testen_xx settings. both 30026-ac 30036-ad 30126-bc 30136-bd [0] testmode_xx 00 serdes test mode select, channel xx. testmode_xx = 0 selects near end loopback (cml tx to cml rx internally) testmode_xx = 1 selects far end loopback (cml rx to cml tx internally) factory test [1:7] rsvd reserved, set to zero (default).
lattice semiconductor orca orso42g5 and orso82g5 data sheet 81 table 25. serdes per-block control register descriptions ?orso42g5 (0x) absolute address bit name reset value (0x) description mode serdes per-block control register (read/write) xx = [ac, ad, bc, bd] 30005 - a 30105 - b [0] rsvd 44 reserved [1] gmask_[a:b] global mask. when gmask_[a:b] = 1, the transmit and receive alarms of all channel in the serdes block are prevented from gener- ating an alarm (i.e., they are masked or dis- abled). the gmask_[a:b] bit overrides the individual mask_xx bits. gmask_[a:b] = 1 on device reset. both [2] gswrst_[a:b] software reset bit. the gswrst_[a:b] bit provides the same function as the hardware reset for the transmit and receive sections of all four channels, except that the device con- ?uration settings are not affected when gswrst_[a:b] is asserted. this is not a self- clearing bit. once set, this bit must be manu- ally set and cleared. the gswrst_[a:b] bit overrides the individual swrst_xx bits. gswrst_[a:b] = 0 on device reset. both [3] gpwrdnt_[a:b] powerdown transmit function. when gpwrdnt_[a:b] = 1, sections of the transmit hardware for all four channels are powered down. the gpwrdnt_[a:b] bit overrides the individual pwrdnt_xx bits. gpwrdnt_[a:b] = 0 on device reset. both [4] gpwrdnr_[a:b] powerdown receive function. when gpwrdnr_[a:b] = 1, sections of the receive hardware for all four channels are powered down. the gpwrdnr_[a:b] bit overrides the individual pwrdnr_xx bits. gpwrdnr_[a:b] = 0 on device reset. both [5:6] rsvd reserved [7] gtesten_[a:b] global test enable bit. when gtesten_[a:b] = 1, the transmit and receive sections of all channels in the block are place in test mode. the testmode_xx bits (30026, 30126, etc.) must be set to specify the desired test on a per-channel basis. the gtesten_[a:b] bits override the individual testen_xx settings. factory
lattice semiconductor orca orso42g5 and orso82g5 data sheet 82 table 26. per-channel control register descriptions ?orso42g5 (0x) absolute address bit name reset value (0x) description mode per-channel control register (read/write) xx = ac, ad, bc, bd 30820 - ac 30830 - ad 30920 - bc 30930 - bd [0:4] rsvd 00 reserved [5] cell_align_err_en_xx ? = alarm enabled for cell_align_err_xx cell [6] tx_urun_err_en_xx ? = alarm enabled for tx_urun_err_xx cell [7] tx_orun_err_en_xx ? = alarm enabled for tx_orun_err_xx cell 30821 - ac 30831 - ad 30921 - bc 30931 - bd [0] rsvd 00 reserved [1] oof_en_xx ? = alarm enabled for oof_xx both [2] ex_seq_err_en_xx ? = alarm enabled for ex_seq_err _xx cell [3] seq_err_en_xx ? = alarm enabled for seq_err _xx cell [4] cell_bip_err_en_xx ? = alarm enabled for cell_bip_err_xx cell [5] b1_err_en_xx ? = alarm enabled for b1_err_xx both [6] rx_fifo_ovrun_en_xx ? = alarm enabled for rx_fifo_ovrun_xx cell [7] rdi_en_xx ? = alarm enabled for rdi_xx both 30822 - ac 30832 - ad 30922 - bc 30932 - bd [0] enable_just_xx 00 enable_just_xx =1 causes the core to inter- pret pointer bytes for positive or negative justi? cation sonet [1] fmpu_str_en_xx fmpu_str_en_xx = 1 enables a channel for alignment within a multi-channel alignment group sonet [2:3] fmpu_synmode_xx ?0 - no channel alignment ?1 - twin channel alignment ?0 - 4 channel alignment ?1 - by-8 alignment sonet [4] dscr_inh_xx descrambling inhibit, dscr_inh = 1 inhibits descrambling (in the rx direction) and scram- bling (in the tx direction). when inhibiting the scrambler and descrambler the auto_b1_xx calculated and checked b1 value will always be incorrect. both [5] ffrm_en_xx fast frame enable, ffrm_en=1 enables the fast frame mode. both [6] ais_on_xx alarm indication signal (control), ais_on =1 forces ais-l insertion. both [7] ais_on_oof_xx alarm indication signal on out of frame, ais_on_oof =1 forces ais-l insertion during oof =1. both
lattice semiconductor orca orso42g5 and orso82g5 data sheet 83 30823 - ac 30833 - ad 30923 - bc 30933 - bd [0] bypass_algn_fifo_xx 00 bypass alignment fifo =1 in rx path in sonet mode. dout_xx data is clocked off rwckxx. sonet [1] serdes_only_mode_xx serdes-only mode. serdes_only_mode =1 bypasses all the sonet and cell functions. data is sent directly from the serdes to the fpga logic in the rx path and is passed directly from the fpga logic to the serdes in the tx path. serdes only [2] force_b1_err_xx force b1 error. force_b1_err =1 forces a section b1 error (bit interleaved parity error) in the tx path. valid only when the corresponding auto_toh_xx bit or auto_b1_xx bit is set to one. both [3] force_bip8_err_xx force bip8 error, force_bip8_err =1 forces cell bip8 error in the tx path. cell [4] force_a1a2_err_xx force a1a2 error, force_a1a2_err =1 forces an error in a1a2 bytes (framing error) in the tx path. valid only when the corresponding auto_toh_xx bit or auto_a1a2_xx bit is set to one. both [5] force_ex_seq_err_xx force excessive sequence errors. force_exp_seq_err_xx = 1 forces sequence errors in the tx path by inverting the link header byte sequence number. cell [6] force_seq_err_xx force sequence error, force_seq_err =1 forces one sequence error in the tx path. after this bit is set, the next link header bytes sequence number is inverted. the link header after the errored link header byte will have the correct sequence number cell [7] force_rdi_xx force remote defect indication, force_rdi =1 forces rdi errors in the tx path. the k2 byte in toh is set to ?0000110. valid only when auto_toh_xx bit is set to 1. cell table 26. per-channel control register descriptions ?orso42g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 84 30824 - ac 30834 - ad 30924 - bc 30934 - bd [0] lckrefn_xx 00 0 = lock receiver to reference clock (refclk) 1 = lock receiver to hdinxx data both [1] loopenb_xx loopenb_xx =1 enable high-speed internal loopback from tx to rx. disable the hdout buffers. both [2] disable_tx_xx disable transmitter, for disable_tx = 1 the tx link is disabled. the disabled link is ignored by the output port controller (opc) and inter- nally generated idle cells are transmitted on the link.fif the link is disabled during the transmis- sion of a cell on the link, the entire cell is trans- mitted before the link is declared invalid. cell [3] disable_rx_xx disable receiver, disable_rx = 1 disables the rx link for cell processing by the input port controller (ipc). the ipc will not read cells from a link if this bit is set for that link cell [4] cell_bip_inh_xx cell bip (check) inhibit, cell_bip_inh = 1 prevents cells from being dropped due to a cell bip error, in the rx path. if this bit is not set, then cells will be dropped automatically if a cell bip error is detected by the core. the cell- drop signal across the core-fpga interface will be active only if this bit is not set. cell [5] cell_seq_inh_xx cell sequence (checking) inhibit, cell_seq_inh = 1 prevents cells in the rx path from being dropped due to a sequence error. if this bit is not set, then cells will be dropped automatically if a sequence error is detected internally. the celldrop signal across the core-fpga interface will be active only if this bit is not set. cell [6] auto_toh_xx automatic toh generation, auto_toh_xx =1 enables the tx core to automatically generate toh bytes. all the force_* register bits are valid if this bit is set. this bit should be set to 1 in cell mode. it can be set to 1or 0 in sonet mode. if this bit is not set, then user has to pro- vide all the toh bytes or use the auto_soh mode. sonet [7] fmpu_resync1_xx single channel alignment fifo reset. rising edge sensitive. write a 0 and then a 1 to enable this bit. when enabled, the read pointer in the alignment fifo is reset to the middle of the fifo. this bit is valid only when fmpu_synmode_xx = 00 (no multi channel alignment) sonet 30825 - ac 30835 - ad 30925 - bc 30935 - bd [0:7] link_num_tx_xx 00 transmit link number, this value is transmitted in the ?1 byte of the toh. this value is used to verify that the links are connected properly and is only used in the auto_toh mode. both table 26. per-channel control register descriptions ?orso42g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 85 30826 - ac 30836 - ad 30926 - bc 30936 - bd [0:5] rsvd 00 reserved [6] auto_b1_xx auto_b1_xx = 0, b1 is not inserted by the embedded core auto_b1_xx = 1, b1 is calculated and inserted by the embedded core auto_toh_xx = 1 overrides this bit both [7] auto_a1a2_xx auto_a1a2_xx = 0, a1/a2 bytes are not inserted by the embedded core auto_a1a2_xx = 1, a1/a2 bytes inserted by the embedded core auto_toh_xx = 1 overrides this bit table 26. per-channel control register descriptions ?orso42g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 86 table 27. per-channel status register descriptions ?orso42g5 (0x) absolute address bit name reset value (0x) description mode channel status registers (read only) xx = [ac, ad, bc, bd] 30828 - ac 30838 - ad 30928 - bc 30938 - bd [0:4] rsvd 00 reserved [5] cell_align_err_xx cell alignment error, cell_align_err = 1 indicates that the internal transmit frame pro- cessor did not detect a start of cell indicator when it was expecting a new cell. if the corre- sponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell [6] tx_urun_err_xx transmit underrun error, tx_urun_err = 1 indicates an underrun error in the transmit asynchronous fifo. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell [7] tx_orun_err_xx transmit overrun error, tx_orun_err = 1 indicates an overrun error in the transmit asyn- chronous fifo. the tx fifo is designed to not over?w since it sends backpressure signal to the fpga when it cannot accept more cells. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell 30829 - ac 30839 - ad 30929 - bc 30939 - bd [0] rsvd 00 reserved [1] oof_xx oof_xx = 1 indicates oof has been detected in this link. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm both [2] ex_seq_err_xx excessive sequence errors, ex_seq_err = 1 indicates that three consecutive cells containing sequence errors have been detected in this link. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell [3] seq_err_xx sequence error, seq_err = 1 indicates that a sequence error has been detected for a cell on this link. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell ]4] cell_bip_err_xx cell mode bip error, cell_bip_err = 1 indi- cates that a bip error has been detected in a cell on the link. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell [5] b1_err_xx bit interleaved parity error, b1_err = 1 indi- cates that a section b1 error has been detected on the link.if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. both [6] rx_fifo_ovrun_xx receive fifo overrun, rx_fifo_ovrun_xx = 1 indicates that the asynchronous rx fifo has detected an overrun condition. if the corre- sponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell [7] rdi_xx remote defect indication, rdi = 1 indicates that a rdi has been detected on the link. if the cor- responding alarm enable bit has been set, a 1 on this bit will cause an alarm both
lattice semiconductor orca orso42g5 and orso82g5 data sheet 87 3082a - ac 3083a - ad 3092a - bc 3093a - bd [0:4] rsvd 00 reserved [5] stat_cell_align_err_xx stat_cell_align_err_xx = 1 same as cell_align_err_xx except that a 1 on this bit can not cause an interrupt cell [6] stat_tx_urun_err_xx stat_tx_urun_err_xx = 1 same as tx_urun_err_xx except that a 1 on this bit can not cause an interrupt cell [7] stat_tx_orun_err_xx stat_tx_orun_err_xx = 1 same as tx_orun_err_xx except that a 1 on this bit can not cause an interrupt cell 3082b -ac 3083b - ad 3092b - bc 3093b - bd [0] rsvd 00 reserved [1] stat_oof_xx stat_oof_xx = 1 same as oof_xx except that a 1 on this bit can not cause an interrupt both [2] stat_ex_seq_err_xx stat_ex_seq_err_xx = 1 same as ex_seq_err_xx except that a 1 on this bit can not cause an interrupt cell [3] stat_seq_err_xx stat_seq_err_xx = 1 same as seq_err_xx except that a 1 on this bit can not cause an interrupt cell [4] stat_cell_bip_err_xx stat_cell_bip_err_xx = 1 same as cell_bip_err_xx except that a 1 on this bit can not cause an interrupt cell [5] stat_b1_err_xx stat_b1_err_xx = 1 same as b1_err_xx except that a 1 on this bit can not cause an interrupt both [6] stat_rx_fifo_ovrun_xx stat_rx_fifo_ovrun_xx = 1 same as rx_fifo_ovrun_xx except that a 1 on this bit can not cause an interrupt cell [7] stat_rdi_xx stat_rdi_xx = 1 same as rdi_xx except that a 1 on this bit can not cause an interrupt both 3082c - ac 3083c - ad 3092c - bc 3093c - bd [0:7] link_num_rx_xx 00 link number received that is stored in the f1 byte position of the sonet toh both 3082e - ac 3083e ad 3092e- bc 3093e - bd [0:5] rsvd 00 reserved [6] ch248_sync_xx ch248_sync_xx = 1 indicates that a1a2 bytes have been detected by link xx for multi-channel alignment sonet [7] rx_link_good_xx rx_link_good_xx = 1 indicates that frame has been acquired and the link has been stable. goes high at an a1a2 boundary but can go low at any point in a frame due to excessive errors cell table 27. per-channel status register descriptions ?orso42g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 88 table 28. common control register descriptions ?orso42g5 (0x) absolute address bit name reset value (0x) description mode 30a00 [0:1] rckselb 00 ?0 - channel bc source for clock rck78b ?1 - channel bd source for clock rck78b both [2:3] tckselb ?0 - channel bc source for clock tck78b ?1 - channel bd source for clock tck78b both [4:5] rcksela ?0 - channel ac source for clock rck78a ?1 - channel ad source for clock rck78a both [6:7] tcksela ?0 - channel ac source for clock tck78a ?1 - channel ad source for clock tck78a both 30a01 [0:2] cell_size 00 cell size, three bits to set cell size. ?00 - cell size is 75 bytes, ?01 - cell size is 79 bytes, ?10 - cell size is 83 bytes, ?11 - cell size is 91 bytes these are the only supported cell sizes. cell [3:7] rx_fifo_min set minimum threshold value for alignment fifo in sonet mode. when the read address for the fifo is below this value at the time when write address is zero, it indicates that the fifo is near over?w. this event will go high only once during a frame when a framing byte has been detected by the aligner. the default threshold value is ?0000? sonet 30a02 0 tx_disable_on_rdi 00 transmitter disable on rdi (detection), if tx_disable_on_rdi = 1 - no cell data is transmitted on a link in which a rdi has been detected by the corresponding links receiver. if this bit is set to 0, cell data will be transmitted on a link irrespective of detection of a rdi. cell [1:7] rsvd reserved
lattice semiconductor orca orso42g5 and orso82g5 data sheet 89 30a03 [0] no_tx_rdi_exseq 00 not transmission of rdi, if no_tx_rdi_exseq = 1, a transmit link will not send data if its corresponding receive link is not good due to excessive sequence errors. if this bit is set to 0, a transmit link will still send data even if its corresponding receive link has excessive sequence errors. this bit should always be set during simulation and in sonet mode. both [1] auto_bundle automatic (link) bundle, auto_bundle = 1 allows a link within a link group to remain active even when another link within that group is defective. cell data from all links within that group will continue to be sent to the fpga. if this bit is set to 0, then all links within a link group must be good before cell data are read from the links by the ipc and passed to the fpga. cell [2] rsvd reserved [3] rejoin_a link rejoin, rejoin = 1 forces any link in a serdes block to reassert a ?x link good sig- nal automatically when three consecutive sequence numbers are correct on that link. cell [4] auto_remove_a automatic (link) remove, auto_remove = 1 indicates that any link in a serdes block which sees three excessive sequence errors should deassert the ?x link good signal which will cause the link to be inactive. cell [5] rsvd reserved [6] rejoin_b link rejoin, rejoin = 1 forces any link in a serdes block to reassert a ?x link good sig- nal automatically when three consecutive sequence numbers are correct on that link. cell [7] auto_remove_b auto_remove_b = 1 indicates that any link in serdes block b which sees three excessive sequence errors should deassert the ?x link good signal which will cause the link to be inac- tive. cell 30a04 [0:1] rsvd 00 reserved [2] fmpu_resync2_b2 control to resync channels bc and bd which have been con?ured for multi channel align- ment in sonet mode in block b. requires a ris- ing edge on this bit. write a 0 followed by a 1. sonet [3:4] rsvd reserve sonet [5] fmpu_resync2_a2 control to resync channels ac and ad which have been con?ured for multi channel align- ment in sonet mode in block a. requires a rising edge on this bit. write a 0 followed by a 1. sonet [6] rsvd reserved sonet [7] fmpu_resync4 control to resync all four channels which have been con?ured for multi channel alignment. sonet table 28. common control register descriptions ?orso42g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 90 30a05 [0:2] errcnt_ch 00 error count channel select, control bits to select which channels section b1 error and cell bip error counts are recorded by the bip_err_cnt and cell_bip_err_cnt reg- isters. ?10 - channel ac, ?11 - channel ad, ?10 - channel bc, ?11 - channel bd both [3] rsvd reserved [4] cell_mode_a2 cell mode enable, cell_mode_a2 = 1 enables cell mode for the channel group ac and ad. cell [5] rsvd reserved [6] cell_mode_b2 cell mode enable, cell_mode_b2 = 1 enables cell mode for the channel group bc and bd. cell [7] rsvd reserved 30a06 [0:4] rsvd 00 reserved [5:6] reset_phase reset phase, two bits to select delay phase for delaying the soft reset bit soft_reset with respect to the synchronizing clock. four delay phases can be selected through the values ?0? ?1? ?0 and ?1? both [7] soft_reset soft reset, soft_reset=1 resets the embed- ded core ?p ?ps except for the software regis- ters. this bit does not affect the state of the registers inside the serdes blocks. both 30a07 [0:6] rsvd 00 reserved [7] tx_cfg_done transmitter con?uration done, edge sensitive bit to indicate that all tx con?uration bits are set. after all register bits have been set for transmit direction, write a 0 and then a 1 to this bit. cell 30a08 [0] alarm_status_bd 00 alarm status indicator, this bit is an or of all alarm status bits for the channel bd. a 1 on this bit will also set the alarm pin on the system bus interrupt cause register (on the fpga side). both [1] alarm_status_bc alarm status indicator, this bit is an or of all alarm status bits for the channel bc. a 1 on this bit will also set the alarm pin on the system bus interrupt cause register (on the fpga side). both [2:3] rsvd reserved [4] alarm_status_ad alarm status indicator, this bit is an or of all alarm status bits for the channel ad. a 1 on this bit will also set the alarm pin on the system bus interrupt cause register (on the fpga side). both [5] alarm_status_ac alarm status indicator, this bit is an or of all alarm status bits for the channel ac. a 1 on this bit will also set the alarm pin on the system bus interrupt cause register (on the fpga side). both [6:7] rsvd reserved table 28. common control register descriptions ?orso42g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 91 30a09 [0:7] b1_err_cnt 00 error counter that increments when a section b1 error is detected on a link. the link is selected using errcnt_chsel. this counter is cleared on read. both 30a0a [0:7] cell_bip_err_cnt 00 cell bip error counter, error counter that incre- ments when a cell bip error is detected on a link. the link being monitored is selected using errcnt_chsel. this counter is cleared on read. cell 30a0b [0:2] rsvd 00 reserved [3] cell_drp_b2 cell drop, cell_drp_b2 = 1 indicates that a cell has been dropped from the link group bc and bd cell [4] rsvd reserved [5] cell_drp_a2 cell drop, cell_drp_a2 = 1 indicates that a cell has been dropped from the link group ac and ad cell [6:7] rsvd reserved 30a0c [0:1] rsvd 00 reserved [2] sync2_b2_oos sync2_b2_oos = 1 indicates that channels cannot be aligned within the links bc and bd in sonet mode sonet [3:4] rsvd reserved [5] sync2_a2_oos sync2_a2_oos = 1 indicates that channels cannot be aligned within the ac and ad links in sonet mode sonet [6:7] sync2_a1_oos reserved 30a0d [0:1] rsvd 00 reserved [2] sync2_b2_ovfl sync2_b2_ovfl = 1 indicates that the align- ment fifo(s) in the links bc and bd are near over?w (i.e., at the time of writing into address 0, the read address was less than rx_fifo_min) sonet [3:4] rsvd reserved [5] sync2_a2_ovfl sync2_a2_ovfl = 1 indicates that the align- ment fifo(s) in the links ac and ad are near over?w (i.e., at the time of writing into address 0, the read address was less than rx_fifo_min) sonet [6:7] rsvd reserved 30a0e [0:2] rsvd 00 reserved [3] bdl_align_err_b2 alignment error, bdl_align_err = 1 indi- cates that an alignment error has occurred in the link group pairs bc and bd cell [4] rsvd reserved [5] bdl_align_err_a2 alignment error, bdl_align_err = 1 indi- cates that an alignment error has occurred in the link group pairs ac and ad cell [6:7] rsvd reserved table 28. common control register descriptions ?orso42g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 92 table 29. serdes alarm and alarm mask register descriptions ?orso82g5 table 30. serdes per-channel transmit con?uration register descriptions ?orso82g5 (0x) absolute address bit name reset value (0x) description mode serdes alarm registers (read only) xx = [aa,...,bd] 30000 - aa 30010 - ab 30020 - ac 30030 - ad 30100 - ba 30110 - bb 30120 - bc 30130 - bd [0] rsvd 00 reserved - may be non-zero [1] lki_xx receive pll lock indication, channel xx. lki_xx = 1 indicates the receive pll is locked. note that the pll can either lock to the incom- ing data or to reclk_[a:b]. if the pll is locked to data and the data stream is terminated, lki_xx will go low until the pll locks to refclk_[a:b]. both [2:7] rsvd reserved - may be non-zero serdes alarm mask registers (read/write) xx = [aa,...,bd] 30001 - aa 30011 - ab 30021 - ac 30031 - ad 30101 - ba 30111 - bb 30121 - bc 30131 - bd [0] rsvd ff reserved [1] mlki_xx mask receive pll lock indication, channel mlki_xx = 1 indicates lki_xx is enabled both [2:7] rsvd reserved (0x) absolute address bit name reset value (0x) description mode serdes transmit per-channel con?uration registers (read/write) xx = [aa,...,bd] 30002 - aa 30012 - ab 30022 - ac 30032 - ad 30102 - ba 30112 - bb 30122 - bc 30132 - bd [0] txhr_xx 00 transmit half rate selection bit, channel xx. when txhr_xx = 1, hdout_xx's baud rate = (refclk[a:b]*8) and tck78[a:b] =(ref- clk[a:b]/4); when txhr_xx=0, hdout_xx's baud rate = (refclk[a:b]*16) and tck78[a:b]=(refclk[a:b]/2). txhr_xx = 0 on device reset. both [1] pwrdnt_xx transmit powerdown control bit, channel xx. when pwrdnt_xx = 1, sections of the trans- mit hardware are powered down. pwrdnt_xx = 0 on device reset. both [2] pe0_xx transmit preemphasis selection bit 0, channel xx. pe0_xx and pe1_xx select one of three pre- emphasis settings for the transmit section. peo_xx=pe1_xx = 0, preemphasis is 0% peo_xx=1, pe1_xx = 0 or peo_xx=0, pe1_xx = 1, preemphasis is 12.5% peo_xx=pe1_xx = 1, preemphasis is 25%. peo_xx=pe1_xx = 0 on device reset. both [3] pe1_xx both [4] hamp_xx transmit half amplitude selection bit, channel xx. when hamp_xx = 1, the transmit output buffer voltage swing is limited to half its normal amplitude. otherwise, the transmit output buffer maintains its full voltage swing. hamp_xx = 0 on device reset. both [5:7] rsvd reserved, always set to ?00
lattice semiconductor orca orso42g5 and orso82g5 data sheet 93 table 31. serdes per-channel receive con?uration register descriptions ?orso82g5 table 32. serdes common con?uration register descriptions ?orso82g5 (0x) absolute address bit name reset value (0x) description mode serdes receive per-channel con?uration registers (read/write) xx = [aa,...,bd] 30003 - aa 30013 - ab 30023 - ac 30033 - ad 30103 - ba 30113 - bb 30123 - bc 30133 - bd [0] rxhr_xx 20 receive half rate selection bit, channel xx. when rxhr_xx =1, hdin_xx's baud rate = (refclk[a:b]*8) and rck78[a:b]=(ref- clk[a:b]/4); when rxhr_xx=0, hdin_xx's baud rate = (refclk[a:b]*16) and rck78[a:b]=(refclk/2). rxhr_xx = 0 on device reset. both [1] pwrdnr_xx receiver power down control bit, channel xx. when pwrdnr_xx = 1, sections of the receive hardware are powered down. pwrdnr_xx = 0 on device reset. both [2:7] rsvd reserved (bit 2 = 1 on device reset) (0x) absolute address bit name reset value (0x) description mode serdes common transmit and receive channel con?uration registers (read/write) xx = [aa,...,bd] 30004 - aa 30014 -ab 30024 - ac 30034 - ad 30104 - ba 30114 - bb 30124 - bc 30134 - bd [0] rsvd 40 reserved [1] mask_xx transmit and receive alarm mask bit, channel xx. when mask_xx = 1, the transmit and receive alarms of a channel are prevented from generating an alarm (i.e., they are masked or disabled). the mask_xx bit overrides the indi- vidual alarm mask bits in the alarm mask reg- isters. mask_xx = 1 on device reset. both [2] swrst_xx transmit and receive software reset bit, channel xx. when swrst_xx = 1, this bit pro- vides the same function as the hardware reset, except that all con?uration register settings are unaltered. this is not a self-clearing bit. once set, this bit must be manually set and cleared. swrst = 0 on device reset. both [3:6] rsvd reserved [7] testen_xx transmit and receive test enable bit, channel xx. when testen_xx = 1, the transmit and receive sections of channel xx are place in test mode. the testmode_xx bits (30006, 30106, etc.) must be set to specify the desired test. the gtesten_[a:b] bits override the individual testen_xx settings. both 30006-aa 30016-ab 30026-ac 30036-ad 30106-ba 30116-bb 30126-bc 30136-bd [0] testmode_xx 00 serdes test mode select, channel xx. testmode_xx = 0 selects far end loopback (cml tx to cml rx internally) testmode_xx = 1 selects near end loopback (cml rx to cml tx internally) factory test [1:7] rsvd reserved, set to zero (default).
lattice semiconductor orca orso42g5 and orso82g5 data sheet 94 table 33. serdes per-block control register descriptions ?orso82g5 (0x) absolute address bit name reset value (0x) description mode serdes per-block control register (read/write) xx = [aa,...,bd] 30005 - a 30105 - b [0] rsvd 44 reserved [1] gmask_[a:b] global mask. when gmask_[a:b] = 1, the transmit and receive alarms of all channel in the serdes block are prevented from gener- ating an alarm (i.e., they are masked or dis- abled). the gmask_[a:b] bit overrides the individual mask_xx bits. gmask_[a:b] = 1 on device reset. both [2] gswrst_[a:b] software reset bit. the gswrst_[a:b] bit provides the same function as the hardware reset for the transmit and receive sections of all four channels, except that the device con- ?uration settings are not affected when gswrst_[a:b] is asserted. this is not a self- clearing bit. once set, this bit must be manu- ally set and cleared. the gswrst_[a:b] bit overrides the individual swrst_xx bits. gswrst_[a:b] = 0 on device reset. both [3] gpwrdnt_[a:b] powerdown transmit function. when gpwrdnt_[a:b] = 1, sections of the transmit hardware for all four channels are powered down. the gpwrdnt_[a:b] bit overrides the individual pwrdnt_xx bits. gpwrdnt_[a:b] = 0 on device reset. both [4] gpwrdnr_[a:b] powerdown receive function. when gpwrdnr_[a:b] = 1, sections of the receive hardware for all four channels are powered down. the gpwrdnr_[a:b] bit overrides the individual pwrdnr_xx bits. gpwrdnr_[a:b] = 0 on device reset. both [5:6] rsvd reserved [7] gtesten_[a:b] global test enable bit. when gtesten_[a:b] = 1, the transmit and receive sections of all channels in the block are place in test mode. the testmode_xx bits (30006, 30106, etc.) must be set to specify the desired test on a per-channel basis. the gtesten_[a:b] bits override the individual testen_xx settings. factory
lattice semiconductor orca orso42g5 and orso82g5 data sheet 95 table 34. per-channel control register descriptions ?orso82g5 (0x) absolute address bit name reset value (0x) description mode 30800 - aa 30810 - ab 30820 - ac 30830 - ad 30900 - ba 30910 - bb 30920 - bc 30930 - bd [0:4] rsvd 00 reserved [5] cell_align_err_en_xx ? = alarm enabled for cell_align_err_xx cell [6] tx_urun_err_en_xx ? = alarm enabled for tx_urun_err_xx cell [7] tx_orun_err_en_xx ? = alarm enabled for tx_orun_err_xx cell 30801 - aa 30811 - ab 30821 - ac 30831 - ad 30901 - ba 30911 - bb 30921 - bc 30931 - bd [0] rsvd 00 reserved [1] oof_en_xx ? = alarm enabled for oof_xx both [2] ex_seq_err_en_xx ? = alarm enabled for ex_seq_err _xx cell [3] seq_err_en_xx ? = alarm enabled for seq_err _xx cell [4] cell_bip_err_en_xx ? = alarm enabled for cell_bip_err_xx cell [5] b1_err_en_xx ? = alarm enabled for b1_err_xx both [6] rx_fifo_ovrun_en_xx ? = alarm enabled for rx_fifo_ovrun_xx cell [7] rdi_en_xx ? = alarm enabled for rdi_xx both 30802 - aa 30812 - ab 30822 - ac 30832 - ad 30902 - ba 30912 - bb 30922 - bc 30932 - bd [0] enable_just_xx 00 enable_just_xx =1 causes the core to inter- pret pointer bytes for positive or negative justi? cation sonet [1] fmpu_str_en_xx fmpu_str_en_xx = 1 enables a channel for alignment within a multi-channel alignment group sonet [2:3] fmpu_synmode_xx ?0 - no channel alignment ?1 - twin channel alignment ?0 - 4 channel alignment ?1 - by-8 alignment sonet [4] dscr_inh_xx descrambling inhibit, dscr_inh = 1 inhibits descrambling (in the rx direction) and scram- bling (in the tx direction). when inhibiting the scrambler and descrambler the auto_b1_xx calculated and checked b1 value will always be incorrect. both [5] ffrm_en_xx fast frame enable, ffrm_en=1 enables the fast frame mode. both [6] ais_on_xx alarm indication signal (control), ais_on =1 forces ais-l insertion. both [7] ais_on_oof_xx alarm indication signal on out of frame, ais_on_oof =1 forces ais-l insertion during oof =1. both
lattice semiconductor orca orso42g5 and orso82g5 data sheet 96 30803 - aa 30813 - ab 30823 - ac 30833 - ad 30903 - ba 30913 - bb 30923 - bc 30933 - bd [0] bypass_algn_fifo_xx 00 bypass alignment fifo =1 in rx path in sonet mode. dout_xx data is clocked off rwckxx. sonet [1] serdes_only_mode_xx serdes-only mode. serdes_only_mode =1 bypasses all the sonet and cell functions. data is sent directly from the serdes to the fpga logic in the rx path and is passed directly from the fpga logic to the serdes in the tx path. serdes only [2] force_b1_err_xx force b1 error. force_b1_err =1 forces a section b1 error (bit interleaved parity error) in the tx path. valid only when the corresponding auto_toh_xx bit or auto_b1_xx bit is set to one. both [3] force_bip8_err_xx force bip8 error, force_bip8_err =1 forces cell bip8 error in the tx path. cell [4] force_a1a2_err_xx force a1a2 error, force_a1a2_err =1 forces an error in a1a2 bytes (framing error) in the tx path. valid only when the corresponding auto_toh_xx bit or auto_a1a2_xx bit is set to one. both [5] force_ex_seq_err_xx force excessive sequence errors. force_exp_seq_err_xx = 1 forces sequence errors in the tx path by inverting the link header byte sequence number. cell [6] force_seq_err_xx force sequence error, force_seq_err =1 forces one sequence error in the tx path. after this bit is set, the next link header bytes sequence number is inverted. the link header after the errored link header byte will have the correct sequence number cell [7] force_rdi_xx force remote defect indication, force_rdi =1 forces rdi errors in the tx path. the k2 byte in toh is set to ?0000110? valid only when auto_toh_xx bit is set to 1. cell table 34. per-channel control register descriptions ?orso82g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 97 30804 - aa 30814 - ab 30824 - ac 30834 - ad 30904 - ba 30914 - bb 30924 - bc 30934 - bd [0] lckrefn_xx 00 0 = lock receiver to reference clock (refclk) 1 = lock receiver to hdinxx data both [1] loopenb_xx loopenb_xx =1 enable high-speed internal loopback from tx to rx. disable the hdout buffers. both [2] disable_tx_xx disable transmitter, for disable_tx = 1 the tx link is disabled. the disabled link is ignored by the output port controller (opc) and inter- nally generated idle cells are transmitted on the link.fif the link is disabled during the transmis- sion of a cell on the link, the entire cell is trans- mitted before the link is declared invalid. cell [3] disable_rx_xx disable receiver, disable_rx = 1 disables the rx link for cell processing by the input port controller (ipc). the ipc will not read cells from a link if this bit is set for that link cell [4] cell_bip_inh_xx cell bip (check) inhibit, cell_bip_inh = 1 prevents cells from being dropped due to a cell bip error, in the rx path. if this bit is not set, then cells will be dropped automatically if a cell bip error is detected by the core. the cell- drop signal across the core-fpga interface will be active only if this bit is not set. cell [5] cell_seq_inh_xx cell sequence (checking) inhibit, cell_seq_inh = 1 prevents cells in the rx path from being dropped due to a sequence error. if this bit is not set, then cells will be dropped automatically if a sequence error is detected internally. the celldrop signal across the core-fpga interface will be active only if this bit is not set. cell [6] auto_toh_xx automatic toh generation, auto_toh_xx =1 enables the tx core to automatically generate toh bytes. all the force_* register bits are valid if this bit is set. this bit should be set to 1 in cell mode. it can be set to 1or 0 in sonet mode. if this bit is not set, then user has to pro- vide all the toh bytes or use the auto_soh mode. sonet [7] fmpu_resync1_xx single channel alignment fifo reset. rising edge sensitive. write a 0 and then a 1 to enable this bit. when enabled, the read pointer in the alignment fifo is reset to the middle of the fifo. this bit is valid only when fmpu_synmode_xx = 00 (no multi channel alignment) sonet 30805 - aa 30815 - ab 30825 - ac 30835 - ad 30905 - ba 30915 - bb 30925 - bc 30935 - bd [0:7] link_num_tx_xx 00 transmit link number, this value is transmitted in the ?1 byte of the toh. this value is used to verify that the links are connected properly and is only used in the auto_toh mode. both table 34. per-channel control register descriptions ?orso82g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 98 30806 - aa 30816 - ab 30826 - ac 30836 - ad 30906 - ba 30916 - bb 30926 - bc 30936 - bd [0:5] rsvd 00 reserved [6] auto_b1_xx auto_b1_xx = 0, b1 is not inserted by the embedded core auto_b1_xx = 1, b1 is calculated and inserted by the embedded core auto_toh_xx = 1 overrides this bit both [7] auto_a1a2_xx auto_a1a2_xx = 0, a1/a2 bytes are not inserted by the embedded core auto_a1a2_xx = 1, a1/a2 bytes inserted by the embedded core auto_toh_xx = 1 overrides this bit table 35. per-channel status register descriptions ?orso82g5 (0x) absolute address bit name reset value (0x) description mode channel status registers (read only) xx = [aa,...,bd] 30808 - aa 30818 - ab 30828 - ac 30838 - ad 30908 - ba 30918 - bb 30928 - bc 30938 - bd [0:4] rsvd 00 reserved [5] cell_align_err_xx cell alignment error, cell_align_err = 1 indicates that the internal transmit frame pro- cessor did not detect a start of cell indicator when it was expecting a new cell. if the corre- sponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell [6] tx_urun_err_xx transmit underrun error, tx_urun_err = 1 indicates an underrun error in the transmit asynchronous fifo. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell [7] tx_orun_err_xx transmit overrun error, tx_orun_err = 1 indicates an overrun error in the transmit asyn- chronous fifo. the tx fifo is designed to not over?w since it sends backpressure signal to the fpga when it cannot accept more cells. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell table 34. per-channel control register descriptions ?orso82g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 99 30809 - aa 30819 - ab 30829 - ac 30839 - ad 30909 - ba 30919 - bb 30929 - bc 30939 - bd [0] rsvd 00 reserved [1] oof_xx oof_xx = 1 indicates oof has been detected in this link. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm both [2] ex_seq_err_xx excessive sequence errors, ex_seq_err = 1 indicates that three consecutive cells containing sequence errors have been detected in this link. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell [3] seq_err_xx sequence error, seq_err = 1 indicates that a sequence error has been detected for a cell on this link. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell ]4] cell_bip_err_xx cell mode bip error, cell_bip_err = 1 indi- cates that a bip error has been detected in a cell on the link. if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell [5] b1_err_xx bit interleaved parity error, b1_err = 1 indi- cates that a section b1 error has been detected on the link.if the corresponding alarm enable bit has been set, a 1 on this bit will cause an alarm. both [6] rx_fifo_ovrun_xx receive fifo overrun, rx_fifo_ovrun_xx = 1 indicates that the asynchronous rx fifo has detected an overrun condition. if the corre- sponding alarm enable bit has been set, a 1 on this bit will cause an alarm. cell [7] rdi_xx remote defect indication, rdi = 1 indicates that a rdi has been detected on the link. if the cor- responding alarm enable bit has been set, a 1 on this bit will cause an alarm both 3080a - aa 3081a - ab 3082a - ac 3083a - ad 3090a -ba 3091a - bb 3092a - bc 3093a - bd [0:4] rsvd 00 reserved [5] stat_cell_align_err_xx stat_cell_align_err_xx = 1 same as cell_align_err_xx except that a 1 on this bit can not cause an interrupt cell [6] stat_tx_urun_err_xx stat_tx_urun_err_xx = 1 same as tx_urun_err_xx except that a 1 on this bit can not cause an interrupt cell [7] stat_tx_orun_err_xx stat_tx_orun_err_xx = 1 same as tx_orun_err_xx except that a 1 on this bit can not cause an interrupt cell table 35. per-channel status register descriptions ?orso82g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 100 3080b - aa 3081b - ab 3082b -ac 3083b - ad 3090b - ba 3091b - bb 3092b - bc 3093b - bd [0] rsvd 00 reserved [1] stat_oof_xx stat_oof_xx = 1 same as oof_xx except that a 1 on this bit can not cause an interrupt both [2] stat_ex_seq_err_xx stat_ex_seq_err_xx = 1 same as ex_seq_err_xx except that a 1 on this bit can not cause an interrupt cell [3] stat_seq_err_xx stat_seq_err_xx = 1 same as seq_err_xx except that a 1 on this bit can not cause an interrupt cell [4] stat_cell_bip_err_xx stat_cell_bip_err_xx = 1 same as cell_bip_err_xx except that a 1 on this bit can not cause an interrupt cell [5] stat_b1_err_xx stat_b1_err_xx = 1 same as b1_err_xx except that a 1 on this bit can not cause an interrupt both [6] stat_rx_fifo_ovrun_xx stat_rx_fifo_ovrun_xx = 1 same as rx_fifo_ovrun_xx except that a 1 on this bit can not cause an interrupt cell [7] stat_rdi_xx stat_rdi_xx = 1 same as rdi_xx except that a 1 on this bit can not cause an interrupt both 3080c - aa 3081c - ab 3082c - ac 3083c - ad 3090c - ba 3091c - bb 3092c - bc 3093c - bd [0:7] link_num_rx_xx 00 link number received that is stored in the f1 byte position of the sonet toh both 3080e - aa 3081e - ab 3082e - ac 3083e ad 3090e - ba 3091e - bb 3092e- bc 3093e - bd [0:5] rsvd 00 reserved [6] ch248_sync_xx ch248_sync_xx = 1 indicates that a1a2 bytes have been detected by link xx for multi-channel alignment sonet [7] rx_link_good_xx rx_link_good_xx = 1 indicates that frame has been acquired and the link has been stable. goes high at an a1a2 boundary but can go low at any point in a frame due to excessive errors cell table 35. per-channel status register descriptions ?orso82g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 101 table 36. common control register descriptions ?orso82g5 (0x) absolute address bit name reset value (0x) description mode 30a00 [0:1] rckselb 00 ?0 - channel ba source for clock rck78b ?1 - channel bb source for clock rck78b ?0 - channel bc source for clock rck78b ?1 - channel bd source for clock rck78b both [2:3] tckselb ?0 - channel ba source for clock tck78b ?1 - channel bb source for clock tck78b ?0 - channel bc source for clock tck78b ?1 - channel bd source for clock tck78b both [4:5] rcksela ?0 - channel aa source for clock rck78a ?1 - channel ab source for clock rck78a ?0 - channel ac source for clock rck78a ?1 - channel ad source for clock rck78a both [6:7] tcksela ?0 - channel aa source for clock tck78a ?1 - channel ab source for clock tck78a ?0 - channel ac source for clock tck78a ?1 - channel ad source for clock tck78a both 30a01 [0:2] cell_size 00 cell size, three bits to set cell size. ?00 - cell size is 75 bytes, ?01 - cell size is 79 bytes, ?10 - cell size is 83 bytes, ?11 - cell size is 91 bytes these are the only supported cell sizes. cell [3:7] rx_fifo_min set minimum threshold value for alignment fifo in sonet mode. when the read address for the fifo is below this value at the time when write address is zero, it indicates that the fifo is near over?w. this event will go high only once during a frame when a framing byte has been detected by the aligner. the default threshold value is ?0000? sonet 30a02 0 tx_disable_on_rdi 00 transmitter disable on rdi (detection), if tx_disable_on_rdi = 1 - no cell data is transmitted on a link in which a rdi has been detected by the corresponding links receiver. if this bit is set to 0, cell data will be transmitted on a link irrespective of detection of a rdi. cell [1:3] rsvd reserved 4 schar_ena schar_ena = 1 enables serdes character- ization of serdes b. refer to section factory test 5 schar_txsel schar_txsel =1 is a select tx option which will cause chip ports to directly control the ser- des low-speed transmit ports of one of the channels selected by schar_chan factory test 6:7 schar_chan ?0 - select channel ba to test ?1 - select channel bb to test ?0 - select channel bc to test ?1 - select channel bd to test factory test
lattice semiconductor orca orso42g5 and orso82g5 data sheet 102 30a03 [0] no_tx_rdi_exseq 00 not transmission of rdi, if no_tx_rdi_exseq = 1, a transmit link will not send data if its corresponding receive link is not good due to excessive sequence errors. if this bit is set to 0, a transmit link will still send data even if its corresponding receive link has excessive sequence errors. this bit should always be set during simulation and in sonet mode. both [1] auto_bundle automatic (link) bundle, auto_bundle = 1 allows a link within a link group to remain active even when another link within that group is defective. cell data from all links within that group will continue to be sent to the fpga. if this bit is set to 0, then all links within a link group must be good before cell data are read from the links by the ipc and passed to the fpga. cell [2] rsvd reserved [3] rejoin_a link rejoin, rejoin = 1 forces any link in a serdes block to reassert a ?x link good sig- nal automatically when three consecutive sequence numbers are correct on that link. cell [4] auto_remove_a automatic (link) remove, auto_remove = 1 indicates that any link in a serdes block which sees three excessive sequence errors should deassert the ?x link good signal which will cause the link to be inactive. cell [5] rsvd reserved [6] rejoin_b link rejoin, rejoin = 1 forces any link in a serdes block to reassert a ?x link good sig- nal automatically when three consecutive sequence numbers are correct on that link. cell [7] auto_remove_b auto_remove_b = 1 indicates that any link in serdes block b which sees three excessive sequence errors should deassert the ?x link good signal which will cause the link to be inac- tive. cell table 36. common control register descriptions ?orso82g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 103 30a04 [0] rsvd 00 reserved [1] fmpu_resync4_b control to resync 4 channels which have been con?ured for multi channel alignment in sonet mode in block b. requires a rising edge on this bit. write a 0 followed by a 1. sonet [2] fmpu_resync2_b2 control to resync channels bc and bd which have been con?ured for multi channel align- ment in sonet mode in block b. requires a ris- ing edge on this bit. write a 0 followed by a 1. sonet [3] fmpu_resync2_b1 control to resync channels ba and bb which have been con?ured for multi channel align- ment in sonet mode in block b. requires a ris- ing edge on this bit. write a 0 followed by a 1. sonet [4] fmpu_resync4_a control to resync 4 channels which have been con?ured for multi channel alignment in sonet mode in block a. requires a rising edge on this bit. write a 0 followed by a 1. sonet [5] fmpu_resync2_a2 control to resync channels ac and ad which have been con?ured for multi channel align- ment in sonet mode in block a. requires a rising edge on this bit. write a 0 followed by a 1. sonet [6] fmpu_resync2_a1 control to resync channels aa and ab which have been con?ured for multi channel align- ment in sonet mode in block a. requires a rising edge on this bit. write a 0 followed by a 1. sonet [7] fmpu_resync8 control to resync all 8 channels which have been con?ured for multi channel alignment. sonet table 36. common control register descriptions ?orso82g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 104 30a05 [0:2] errcnt_ch 00 error count channel select, control bits to select which channels section b1 error and cell bip error counts are recorded by the bip_err_cnt and cell_bip_err_cnt reg- isters. ?00 - channel aa, ?01 - channel ab, ?10 - channel ac, ?11 - channel ad, ?00 - channel ba, ?01 - channel bb, ?10 - channel bc, ?11 - channel bd both [3] cell_mode_a1 cell mode enable, cell_mode_a1 = 1 enables cell mode for the channel group aa and ab. cell [4] cell_mode_a2 cell mode enable, cell_mode_a2 = 1 enables cell mode for the channel group ac and ad. cell [5] cell_mode_b1 cell mode enable, cell_mode_b1 = 1 enables cell mode for the channel group ba and bb. cell [6] cell_mode_b2 cell mode enable, cell_mode_b2 = 1 enables cell mode for the channel group bc and bd. cell [7] cell_mode_all cell mode enable, cell_mode_all = 1 enables cell mode for 8-link cell mode. cell_mode_[a1,a2,b1,b2] bits are not valid. cell 30a06 [0:4] rsvd 00 reserved [5:6] reset_phase reset phase, two bits to select delay phase for delaying the soft reset bit soft_reset with respect to the synchronizing clock. four delay phases can be selected through the values ?0? ?1? ?0 and ?1? both [7] soft_reset soft reset, soft_reset=1 resets the embed- ded core ?p ?ps except for the software regis- ters. this bit does not affect the state of the registers inside the serdes blocks. both 30a07 [0:6] rsvd 00 reserved [7] tx_cfg_done transmitter con?uration done, edge sensitive bit to indicate that all tx con?uration bits are set. after all register bits have been set for transmit direction, write a 0 and then a 1 to this bit. cell table 36. common control register descriptions ?orso82g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 105 30a08 [0] alarm_status_bd 00 alarm status indicator, this bit is an or of all alarm status bits for the channel bd. a 1 on this bit will also set the alarm pin on the system bus interrupt cause register (on the fpga side). both [1] alarm_status_bc alarm status indicator, this bit is an or of all alarm status bits for the channel bc. a 1 on this bit will also set the alarm pin on the system bus interrupt cause register (on the fpga side). both [2] alarm_status_bb alarm status indicator, this bit is an or of all alarm status bits for the channel bb. a 1 on this bit will also set the alarm pin on the system bus interrupt cause register (on the fpga side). both [3] alarm_status_ba alarm status indicator, this bit is an or of all alarm status bits for the channel ba. a 1 on this bit will also set the alarm pin on the system bus interrupt cause register (on the fpga side). both [4] alarm_status_ad alarm status indicator, this bit is an or of all alarm status bits for the channel ad. a 1 on this bit will also set the alarm pin on the system bus interrupt cause register (on the fpga side). both [5] alarm_status_ac alarm status indicator, this bit is an or of all alarm status bits for the channel ac. a 1 on this bit will also set the alarm pin on the system bus interrupt cause register (on the fpga side). both [6] alarm_status_ab or of all alarm status bits for channel ab. a 1 on this bit will set the alarm pin on the system bus interrupt cause register (on the fpga side) both [7] alarm_status_aa alarm status indicator, this bit is an or of all alarm status bits for the channel aa. a 1 on this bit will also set the alarm pin on the system bus interrupt cause register (on the fpga side). both 30a09 [0:7] b1_err_cnt 00 error counter that increments when a section b1 error is detected on a link. the link is selected using errcnt_chsel. this counter is cleared on read. both 30a0a [0:7] cell_bip_err_cnt 00 cell bip error counter, error counter that incre- ments when a cell bip error is detected on a link. the link being monitored is selected using errcnt_chsel. this counter is cleared on read. cell table 36. common control register descriptions ?orso82g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 106 30a0b [0:2] rsvd 00 reserved [3] cell_drp_b2 cell drop, cell_drp_b2 = 1 indicates that a cell has been dropped from the link group bc and bd cell [4] cell_drp_b1 cell drop, cell_drp_b1 = 1 indicates that a cell has been dropped from the link group bb and ba cell [5] cell_drp_a2 cell drop, cell_drp_a2 = 1 indicates that a cell has been dropped from the link group ac and ad cell [6] cell_drp_a1 cell drop, cell_drp_a1 = 1 indicates that a cell has been dropped from the link group ab and aa cell [7] cell_drp_all8 cell_drp_all8 = 1 indicates that cells have been dropped on link group comprising of all 8 channels cell 30a0c [0] rsvd 00 reserved [1] sync4_b_oos sync4_b_oos = 1 indicates that channels cannot be aligned within the 4 links in block b in sonet mode sonet [2] sync2_b2_oos sync2_b2_oos = 1 indicates that channels cannot be aligned within the links bc and bd in sonet mode sonet [3] sync2_b1_oos sync2_b1_oos = 1 indicates that channels cannot be aligned within the links bb and ba in sonet mode sonet [4] sync4_a_oos sync4_a_oos = 1 indicates that channels cannot be aligned within the 4 links in block a in sonet mode sonet [5] sync2_a2_oos sync2_a2_oos = 1 indicates that channels cannot be aligned within the ac and ad links in sonet mode sonet [6] sync2_a1_oos sync2_a1_oos = 1 indicates that channels cannot be aligned within the ab and ad links in sonet mode sonet [7] sync8_oos sync8_oos = 1 indicates that channels can- not be aligned within the 8 channels in sonet mode sonet table 36. common control register descriptions ?orso82g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 107 30a0d [0] rsvd 00 reserved [1] sync4_b_ovfl sync8_oos = 1 indicates that the alignment fifo(s) in the links in block b are near over?w (i.e., at the time of writing into address 0, the read address was less than rx_fifo_min) sonet [2] sync2_b2_ovfl sync2_b2_ovfl = 1 indicates that the align- ment fifo(s) in the links bc and bd are near over?w (i.e., at the time of writing into address 0, the read address was less than rx_fifo_min) sonet [3] sync2_b1_ovfl sync2_b1_ovfl = 1 indicates that the align- ment fifo(s) in the links ba and bb are near over?w (i.e., at the time of writing into address 0, the read address was less than rx_fifo_min) sonet [4] sync4_a_ovfl sync4_a_ovfl = 1 indicates that the align- ment fifo(s) in the links in block a are near over?w (i.e., at the time of writing into address 0, the read address was less than rx_fifo_min) sonet [5] sync2_a2_ovfl sync2_a2_ovfl = 1 indicates that the align- ment fifo(s) in the links ac and ad are near over?w (i.e., at the time of writing into address 0, the read address was less than rx_fifo_min) sonet [6] sync2_a1_ovfl sync2_a1_ovfl = 1 indicates that the align- ment fifo(s) in the links aa and ab are near over?w (i.e., at the time of writing into address 0, the read address was less than rx_fifo_min) sonet [7] sync8_ovfl sync8_ovfl = 1 indicates that the alignment fifo(s) in eight-links are near over?w (at the time of writing into address 0, the read address was less than rx_fifo_min) sonet 30a0e [0:2] rsvd 00 reserved [3] bdl_align_err_b2 alignment error, bdl_align_err = 1 indi- cates that an alignment error has occurred in the link group pairs bc and bd cell [4] bdl_align_err_b1 alignment error, bdl_align_err = 1 indi- cates that an alignment error has occurred in the link group pairs ba and bb cell [5] bdl_align_err_a2 alignment error, bdl_align_err = 1 indi- cates that an alignment error has occurred in the link group pairs ac and ad cell [6] bdl_align_err_a1 alignment error, bdl_align_err = 1 indi- cates that an alignment error has occurred in the link group pairs aa and ab cell [7] bdl_align_err_all8 bdl_align_err_all8 = 1 -indicates that an alignment error has occurred in cell group of all eight-links cell table 36. common control register descriptions ?orso82g5 (continued) (0x) absolute address bit name reset value (0x) description mode
lattice semiconductor orca orso42g5 and orso82g5 data sheet 108 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series 4 fpscs include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. table 37. absolute maximum ratings recommended operating conditions table 38. recommended operating conditions serdes electrical and timing characteristics table 39. maximum power dissipation parameter symbol min. max. units storage temperature t stg -65 150 ? power supply voltage with respect to ground v dd33 -0.3 4.2 v v ddio -0.3 4.2 v v dd15, v dd_ana, v ddgb -0.3 2.0 v input signal with respect to ground v in v ss - 0.3 v ddio + 0.3 v signal applied to high-impedance output v ss - 0.3 v ddio + 0.3 v maximum package body (soldering) temperature 220 ? parameter symbol min. max. units power supply voltage with respect to ground 1 v dd33 3.0 3.6 v v dd15 1.425 1.575 v input voltages v in v ss - 0.3 v ddio + 0.3 v junction temperature t j -40 125 ? serdes supply voltage v dd_ana, v ddgb 1.425 1.575 v serdes cml i/o supply voltage v dd ib, v dd ob 1.425 1.89 v 1. for fpga recommended operating conditions and electrical characteristics, see the recommended operating conditions and electr ical characteristics tables in the orca series 4 fpga data sheet (or4e04) and technical note tn1036, orca series 4 i/o users guide. fpsc standby currents (iddsb15 and iddsb33) are tested with the embedded core in the powered down state. parameter conditions min. typ. max. 1 units power dissipation orso82g5 serdes, mux/demux, align fifo and i/o (per channel), 1.25 gbit/s 195 mw serdes, mux/demux, align fifo and i/o (per channel), 2.5 gbit/s 225 mw logic active in both sonet and cell modes (per channel) 25 mw logic active only in cell mode (per channel) 10 mw power dissipation orso42g5 serdes, mux/demux, align fifo and i/o (per channel), 1.25 gbit/s 265 mw serdes, mux/demux, align fifo and i/o (per channel), 2.5 gbit/s 295 mw logic active in both sonet and cell modes (per channel) 25 mw logic active only in cell mode (per channel) 10 mw 1. with all channels operating, 1.575v supply.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 109 high speed data transmitter table 40 speci?s serial data output buffer parameters measured on devices with typical and worst case process parameters and over the full range of operation conditions. table 40. serial output timing and levels (cml i/o) transmitter output jitter is a critical parameter to systems with high speed data links. table 41 and table 42 specify the transmitter output jitter for typical and worst case devices over the full range of operating conditions. table 41. channel output jitter (2.7 gbits/s) table 42. channel output jitter (2.5 gbits/s) parameter min. typ. max. units rise time (20% - 80%) 50 80 110 ps fall time (80% - 20%) 50 80 110 ps common mode v dd ob ?0.30 v dd ob ?0.25 v dd ob ?0.15 v differential swing (full amplitude) 1 750 900 1000 mv p-p differential swing (half amplitude) 1 375 450 500 mv p-p output load (external) 86 1. differential swings measured at the end of 3 inches of fr-4 and 12 inches of coax cable. parameter device min. typ. 1 max. 1 units deterministic orso42g5 0.12 0.16 ulp-p orso82g5 0.12 0.16 ulp-p random 2 orso42g5 0.05 0.18 ulp-p orso82g5 0.05 0.08 ulp-p total 3 orso42g5 0.17 0.34 ulp-p orso82g5 0.17 0.24 ulp-p 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., 0 o c to 85 o c, 1.425v to 1.575v supply. 2. wavecrest sia-3000 instrument used to measure one-sigma (rms) random jitter component value. this value is multiplied by 14 t o provide the peak-to-peak value that corresponds to a ber of 10 -12 . 3. total jitter measurement performed with wavecrest sia-3000 at a ber of 10 -12 . see instrument documentation and other wavecrest publi- cations for a detailed discussion of jitter types included in this measurement. parameter device min. typ. 1 max. 1 units deterministic orso42g5 0.11 0.13 ulp-p orso82g5 0.11 0.13 ulp-p random 2 orso42g5 0.05 0.14 ulp-p orso82g5 0.05 0.07 ulp-p total 3 orso42g5 0.16 0.27 ulp-p orso82g5 0.16 0.20 ulp-p 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., 0 o c to 85 o c, 1.425v to 1.575v supply. 2. wavecrest sia-3000 instrument used to measure one-sigma (rms) random jitter component value. this value is multiplied by 14 t o provide the peak-to-peak value that corresponds to a ber of 10 -12 . 3. total jitter measurement performed with wavecrest sia-3000 at a ber of 10 -12 . see instrument documentation and other wavecrest publi- cations for a detailed discussion of jitter types included in this measurement.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 110 high speed data receiver table 43 speci?s receiver parameters measured on devices with worst case process parameters and over the full range of operation conditions. table 43. external data input speci?ations input data jitter tolerance a receiver's ability to tolerate incoming signal jitter is very dependent on jitter type. high speed serial interface stan- dards have recognized the dependency on jitter type and have recently modified specifications to indicate toler- ance levels for different jitter types as they relate to specific protocols. sinusoidal jitter is considered to be a worst case jitter type. table 44 shows receiver specifications with 10 mhz sinusoidal jitter injection. other jitter tolerance measurements were measured in a separate experiment detailed in technical note tn1032, serdes test chip jit- ter, and are not re?cted in these results. table 44. receiver sinusoidal jitter tolerance speci?ations parameter conditions min. typ. max. units input data stream of nontransitions scrambler off 72 bits sensitivity (differential), worst-case 1 2.7gbps 80 mvp-p input levels 2 v ss - 0.3 v dd_ana + 0.3 v internal buffer resistance (each input to vddib) 40 50 60 pll lock time 3 note 2 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., t a = 0 o c to 85 o c, 1.425v to 1.575v sup- ply. 2. input level min + (input peak to peak swing)/2 common mode input voltage input level max - (input peak to peak swing)/2 3. the ort82g5 serdes receiver performs four levels of synchronization on the incoming serial data stream, providing ?st bit, t hen byte (character), then channel (32-bit word), and ?ally optional multi-channel alignment as described in tn1025. the pll lock time is the time required for the cdr pll to lock to the transitions in the incoming high-speed serial data stream. if the pll is unable to lock to the serial data stream, it instead locks to refclk to stabilize the voltage-controlled oscillator (vco), and periodically switches back to the serial data stream to again attempt synchronization. parameter conditions max. unit input data jitter tolerance @ 2.7gbps, typical 600 mv diff eye 1 0.75 u ip-p jitter tolerance @ 2.7gbps, worst case 600 mv diff eye 1 0.65 u ip-p jitter tolerance @ 2.5gbps,typical 600 mv diff eye 1 0.79 u ip-p jitter tolerance @ 2.5gbps, worst case 600 mv diff eye 1 0.67 u ip-p 1. with prbs 2^7-1 data pattern, all channels operating, fpga logic active, refclk jitter of 30 ps., t a = 0 o c to 85 o c, 1.425v to 1.575v supply. jitter measured with a wavecrest sia-3000.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 111 input eye-mask characterization figure 51 provides an eye-mask characterization of the serdes receiver input. the eye-mask is speci?d below for two different eye-mask heights. it provides guidance on a number of input parameters, including signal ampli- tude and rise time limits, noise and jitter limits, and p and n input skew tolerance. almost all detrimental character- istics of transmit signal and the interconnection link design result in eye-closure. this, combined with the eye- opening limitations of the line receiver, can provide a good indication of a links ability to transfer data error-free. the clock and data recovery (cdr) portion of the orso42g5 and orso82g5 serdes receiver has the ability to ?ter incoming signal jitter that is below the clock recovery pll bandwidth (about 3 mhz). the eye-mask speci? cations of table 45 are for jitter frequencies above the pll bandwidth of the cdr, which is a worst case condition. when jitter occurs at frequencies below the pll bandwidth, the receiver jitter tolerance is signi?antly better. for this case error-free data detection can occur even with a completely closed eye-mask. figure 51. receive data eye-diagram template (differential) table 45. receiver eye-mask speci?ations 1 parameter conditions value unit input data eye opening width (h)@ 2.7gbps v=175 mv diff 1 0.55 u ip-p eye opening width (t)@ 2.7gbps v=175 mv diff 1 0.15 u ip-p eye opening width (h)@ 2.7gbps v=600 mv diff 1 0.35 u ip-p eye opening width (t)@ 2.7gbps v=600 mv diff 1 0.10 u ip-p eye opening width (h)@ 2.5gbps v=175 mv diff 1 0.42 u ip-p eye opening width (t)@ 2.5gbps v=175 mv diff 1 0.15 u ip-p eye opening width (h)@ 2.5gbps v=600 mv diff 1 0.33 u ip-p eye opening width (t)@ 2.5gbps v=600 mv diff 1 0.10 u ip-p 1. with prbs 2^7-1 data pattern, 10 mhz sinusoidal jitter, all channels operating, fpga logic active, refclk jitter of 30 ps., t a = 0 o c to 85 o c, 1.425v to 1.575v supply. h v 1.2 v ui t
lattice semiconductor orca orso42g5 and orso82g5 data sheet 112 external reference clock the external reference clock selection and its interface are a critical part of system applications for this product. table 46 speci?s reference clock requirements, over the full range of operating conditions. the designer is encourage to read tn1040, serdes reference clock, which discusses various aspects of this system element and its interconnection. table 46. reference clock speci?ations (refclkp_[a:b] and refclkn_[a:b]) parameter min. typ. max. units frequency range 60 185 mhz frequency tolerance 1 -350 350 ppm duty cycle (measured at 50% amplitude point) 40 50 60 % rise time 500 1000 ps fall time 500 1000 ps p? input skew 75 ps differential amplitude 500 800 2 x v ddib mv p-p common mode level v single-ended/2 0.75 v dd 15 ?(v single-ended/2 ) v single-ended amplitude 250 400 v ddib mv p-p input capacitance (at refclkp_[a:b]) 5 pf input capacitance (at refclkn_[a:b]) 5 pf 1. this speci?ation indicates the capability of the high speed receiver cdr pll to acquire lock when the reference clock frequ ency and incoming data rate are not synchronized.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 113 pin descriptions this section describes the pins found on the series 4 fpgas. any pin not described in this table is a user-program- mable i/o. during con?uration, the user-programmable i/os are 3-stated with an internal pull-up resistor. if any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor after con?uration. the pin descriptions in table 47 and throughout this data sheet show active-low signals with an overscore. the package pinout tables that follow, show this as a signal ending with _n. for example ldc and ldc_n are equiva- lent. table 47. pin descriptions symbol i/o description dedicated pins v dd 33 3.3v positive power supply. this power supply is used for 3.3v con?uration rams and internal plls. when using plls, this power supply should be well isolated from all other power supplies on the board for proper operation. v dd 15 1.5v positive power supply for internal logic. v dd io positive power supply used by i/o banks. v ss ground. ptemp i temperature sensing diode pin. dedicated input. reset i during con?uration, reset forces the restart of con?uration and a pull-up is enabled. after con?uration, reset can be used as a general fpga input or as a direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk o in the master and asynchronous peripheral modes, cclk is an output which strobes con?ura- tion data in. i in the slave or readback after con?uration, cclk is input synchronous with the data on din or d[7:0]. cclk is an output for daisy-chain operation when the lead device is in master, periph- eral, or system bus modes. done i as an input, a low level on done delays fpga start-up after con?uration. 1 o as an active-high, open-drain output, a high level on this signal indicates that con?uration is complete. done has an optional pull-up resistor. prgrm i prgrm is an active-low input that forces the restart of con?uration and resets the boundary- scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during con?uration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after con?uration , rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the con?uration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides con?uration data out. if used in boundary-scan, tdo is test data out. cfg_irq /mpi_irq o during jtag, slave, master, and asynchronous peripheral con?uration assertion on this cfg_irq (active-low) indicates an error or errors for block ram or fpsc initialization. mpi active-low interrupt request output, when the mpi is used. lvds_r reference resistor connection for controlled impedance termination of series 4 fpga lvds inputs. special-purpose pins m[3:0] i during powerup and initialization, m0?3 are used to select the con?uration mode with their values latched on the rising edge of init . during con?uration, a pull-up is enabled. i/o after con?uration, these pins are user-programmable i/o. 1 pll_ck[0:7][tc] i semi-dedicated pll clock pins. during con?uration they are 3-stated with a pull up. i/o these pins are user-programmable i/o pins if not used by plls after con?uration.
lattice semiconductor orca orso42g5 and orso82g5 data sheet 114 p[tblr]clk[1:0][tc] i pins dedicated for the primary clock. input pins on the middle of each side with differential pair- ing. i/o after con?uration these pins are user programmable i/o, if not used for clock inputs. tdi, tck, tms i if boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary-scan is not selected, all boundary-scan functions are inhibited once con?uration is complete. even if boundary-scan is not used, either tck or tms must be held at logic 1 during con?uration. each pin has a pull-up enabled during con?uration. i/o after con?uration, these pins are user-programmable i/o if boundary scan is not used. 1 rdy/b usy /rclk o during con?uration in asynchronous peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same sta- tus is also available on d7 in asynchronous peripheral mode. during the master parallel con?uration mode, rclk is a read output signal to an external memory. this output is not normally used. i/o after con?uration this pin is a user-programmable i/o pin. 1 hdc o high during con?uration is output high until con?uration is complete. it is used as a control output, indicating that con?uration is not complete. i/o after con?uration, this pin is a user-programmable i/o pin. 1 ldc o lo w dur ing con gur ation is output low until con?uration is complete. it is used as a control out- put, indicating that con?uration is not complete. i/o after con?uration, this pin is a user-programmable i/o pin. 1 init i/o init is a bidirectional signal before and during con?uration. during con?uration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of con?uration. after con?uration, this pin is a user-programmable i/o pin. 1 cs0 , cs1 i cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and microprocessor con- ?uration modes. the fpga is selected when cs0 is low and cs1 is high. during con?ura- tion, a pull-up is enabled. i/o after con?uration, if mpi is not used, these pins are user-programmable i/o pins. 1 rd /mpi_strb i rd is used in the asynchronous peripheral con?uration mode. a low on rd changes d[7:3] into a status output. wr and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the mpi data transfer strobe. as a status indication, a high indicates ready, and a low indicates busy. wr /mpi_rw i wr is used in asynchronous peripheral mode. a low on wr transfers data on d[7:0] to the fpga. in mpi mode, a high on mpi_rw allows a read from the data bus, while a low causes a write transfer to the fpga. i/o after con?uration, if the mpi is not used, wr /mpi_rw is a user-programmable i/o pin. 1 ppc_a[14:31] i during mpi mode the ppc_a[14:31] are used as the address bus driven by the powerpc bus master utilizing the least-signi?ant bits of the powerpc 32-bit address. mpi_b urst i mpi_b urst is driven low to indicate a burst transfer is in progress in mpi mode. driven high indicates that the current transfer is not a burst. mpi_bdip i mpi_bdip is driven by the powerpc processor in mpi mode. assertion of this pin indicates that the second beat in front of the current one is requested by the master. negated before the burst transfer ends to abort the burst data phase. mpi_tsz[0:1] i mpi_tsz[0:1] signals are driven by the bus master in mpi mode to indicate the data transfer size for the transaction. set 01 for byte, 10 for half-word, and 00 for word. a[21:0] o during master parallel mode a[21:0] address the con?uration eproms up to 4m bytes. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 table 47. pin descriptions (continued) symbol i/o description
lattice semiconductor orca orso42g5 and orso82g5 data sheet 115 mpi_ack o in mpi mode this is driven low indicating the mpi received the data on the write cycle or returned data on a read cycle. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 mpi_clk i this is the powerpc synchronous, positive-edge bus clock used for the mpi interface. it can be a source of the clock for the embedded system bus. if mpi is used this will be the amba bus clock. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 mpi_tea o a low on the mpi transfer error acknowledge indicates that the mpi detects a bus error on the internal system bus for the current transaction. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 mpi_rtry o this pin requests the mpc860 to relinquish the bus and retry the cycle. i/o if not used for mpi these pins are user-programmable i/o pins after con?uration. 1 d[0:31] i/o selectable data bu s width from 8, 16, 32-bit in mpi mode. driven by the bus master in a write transaction and driven by mpi in a read transaction. i d[7:0] receive con?uration data during master parallel, peripheral, and slave parallel con?u- ration modes when wr is low and each pin has a pull-up enabled. during serial con?uration modes, d0 is the din input. o d[7:3] output internal status for asynchronous peripheral mode when rd is low. i/o after con?uration, if mpi is not used, the pins are user-programmable i/o pins. 1 dp[0:3] i/o selectable parity bus width in mpi mode from 1, 2, 4-bit, dp[0] for d[0:7], dp[1] for d[8:15], dp[2] for d[16:23], and dp[3] for d[24:31]. after con?uration, if mpi is not used, the pins are user-programmable i/o pin. 1 din i during slave serial or master serial con?uration modes, din accepts serial con?uration data synchronous with cclk. during parallel con?uration modes, din is the d0 input. during con- ?uration, a pull-up is enabled. i/o after con?uration, this pin is a user-programmable i/o pin. 1 dout o during con?uration, dout is the serial data output that can drive the din of daisy-chained slave devices. data out on dout changes on the rising edge of cclk. i/o after con?uration, dout is a user-programmable i/o pin. 1 testcfg (orso82g5 only) i during con?uration this pin should be held high, to allow con?uration to occur. a pull up is enabled during con?uration. i/o after con?uration, testcfg is a user programmable i/o pin. 1 1. the fpga states of operation section in the orca series 4 fpgas data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con?uration pins (and the activation of all user i/os) is controlled by a second set of options. table 47. pin descriptions (continued) symbol i/o description
lattice semiconductor orca orso42g5 and orso82g5 data sheet 116 this section describes device i/o signals to/from the embedded core. table 48. fpsc function pin descriptions symbol i/o description common signals for both serdes block a and b pasb_resetn i active low reset for the embedded core. 1 pasb_tristn i active low 3-state for embedded core output buffers. 1 pasb_pdn i active low power down of all serdes blocks and associated i/os. 1 pasb_testclk i clock input for bist and loopback test (factory only). 1 pbist_test_enn i selection of pasb_testclk input for bist test (factory only). 1 ploop_test_enn i digital only loopback from tx to rx (factory only). 1 pmp_testclk i clock input for microprocessor in test mode (factory only). 1 pmp_testclk_enn i selection of pmp_testclk in test mode (factory only). 1 psys_dobistn i input to start bist test (factory only). 1 psys_rssig_all o output result of bist test (factory only). serdes block a and b pins refclkn_a i cml reference clock input?erdes block a. refclkp_a i cml reference clock input?erdes block a. refclkn_b i cml reference clock input?erdes block b. refclkp_b i cml reference clock input?erdes block b. rext_a reference resistor?erdes block a. rext_b reference resistor?erdes block b. rextn_a reference resistor ?serdes block. a 3.32 k w ?1% resistor must be connected across rext_b and rextn_b. this resistor should handle a current of 300 ?. rextn_b reference resistor?erdes block b. a 3.32 k ?1% resistor must be connected across rext_b and rextn_b. this register should handle a current of 300 ? hdinn_aa i high-speed cml receive data input?erdes block a, channel a (not available in orso42g5). hdinp_aa i high-speed cml receive data input?erdes block a, channel a (not available in orso42g5). hdinn_ab i high-speed cml receive data input?erdes block a, channel b (not available in orso42g5). hdinp_ab i high-speed cml receive data input?erdes block a, channel b (not available in orso42g5). hdinn_ac i high-speed cml receive data input?erdes block a, channel c. hdinp_ac i high-speed cml receive data input?erdes block a, channel c. hdinn_ad i high-speed cml receive data input?erdes block a, channel d. hdinp_ad i high-speed cml receive data input?erdes block a, channel d. hdinn_ba i high-speed cml receive data input?erdes block b, channel a. hdinp_ba i high-speed cml receive data input?erdes block b, channel a (not available in orso42g5). hdinn_bb i high-speed cml receive data input?erdes block b, channel b (not available in orso42g5). hdinp_bb i high-speed cml receive data input?erdes block b, channel b (not available in orso42g5). hdinn_bc i high-speed cml receive data input?erdes block b, channel c (not available in orso42g5). hdinp_bc i high-speed cml receive data input?erdes block b, channel c. hdinn_bd i high-speed cml receive data input?erdes block b, channel d. hdinp_bd i high-speed cml receive data input?erdes block b, channel d. serdes block a and b pins hdoutn_aa o high-speed cml transmit data output?erdes block a, channel a (not available in orso42g5). hdoutp_aa o high-speed cml transmit data output?erdes block a, channel a (not available in orso42g5).
lattice semiconductor orca orso42g5 and orso82g5 data sheet 117 hdoutn_ab o high-speed cml transmit data output?erdes block a, channel b (not available in orso42g5). hdoutp_ab o high-speed cml transmit data output?erdes block a, channel b (not available in orso42g5). hdoutn_ac o high-speed cml transmit data output?erdes block a, channel c. hdoutp_ac o high-speed cml transmit data output?erdes block a, channel c. hdoutn_ad o high-speed cml transmit data output?erdes block a, channel d. hdoutp_ad o high-speed cml transmit data output?erdes block a, channel d. hdoutn_ba o high-speed cml transmit data output?erdes block b, channel a (not available in orso42g5). hdoutp_ba o high-speed cml transmit data output?erdes block b, channel a (not available in orso42g5). hdoutn_bb o high-speed cml transmit data output?erdes block b, channel b (not available in orso42g5). hdoutp_bb o high-speed cml transmit data output?erdes block b, channel b (not available in orso42g5). hdoutn_bc o high-speed cml transmit data output?erdes block b, channel c. hdoutp_bc o high-speed cml transmit data output?erdes block b, channel c. hdoutn_bd o high-speed cml transmit data output?erdes block b, channel d. hdoutp_bd o high-speed cml transmit data output?erdes block b, channel d. power and ground v dd ib_aa 1.8v/1.5v power supply for high-speed serial input buffers (orso82g5 only). v dd ib_ab 1.8v/1.5v power supply for high-speed serial input buffers (orso82g5 only). v dd ib_ac 1.8v/1.5v power supply for high-speed serial input buffers. v dd ib_ad 1.8v/1.5v power supply for high-speed serial input buffers. v dd ib_ba 1.8v/1.5v power supply for high-speed serial input buffers (orso82g5 only). v dd ib_bb 1.8v/1.5v power supply for high-speed serial input buffers (orso82g5 only). v dd ib_bc 1.8v/1.5v power supply for high-speed serial input buffers. v dd ib_bd 1.8v/1.5v power supply for high-speed serial input buffers. v dd ob_aa 1.8v/1.5v power supply for high-speed serial output buffers (orso82g5 only). v dd ob_ab 1.8v/1.5v power supply for high-speed serial output buffers (orso82g5 only). v dd ob_ac 1.8v/1.5v power supply for high-speed serial output buffers. v dd ob_ad 1.8v/1.5v power supply for high-speed serial output buffers. v dd ob_ba 1.8v/1.5v power supply for high-speed serial output buffers (orso82g5 only). v dd ob_bb 1.8v/1.5v power supply for high-speed serial output buffers (orso82g5 only). v dd ob_bc 1.8v/1.5v power supply for high-speed serial output buffers. v dd ob_bd 1.8v/1.5v power supply for high-speed serial output buffers. v dd gb_a 1.5v guard band power supply. v dd gb_b 1.5v guard band power supply. v dd _ana 1.5v power supplies for serdes analog transmit and receive circuitry. 1. should be externally connected on board to 3.3v pull-up resistor. table 48. fpsc function pin descriptions (continued) symbol i/o description
lattice semiconductor orca orso42g5 and orso82g5 data sheet 118 power supplies power supply descriptions table 49 shows the orso42g5 and orso82g5 fpgas and embedded core power supply groupings. vdd33 is a 3.3v positive power supply used for 3.3v con?uration rams and internal fpga plls. when using fpga plls, this power supply should be well isolated from all other power supplies on the board for proper operation. the ?e vddio supplies are positive power supply used by the fpga i/o banks.the 1.5 volt digital power supplies are used for the fpga and the embedded core transmit and receive digital logic including the microprocessor logic. the 1.5 volt analog power supply is used for high-speed analog circuitry in the embedded core between the i/o buffers and the digital logic. the rx input buffer power supplies are used to power the input (receive) buffers. the tx output buffer supplies are used to power the output (transmit) buffers. the rx and tx buffer power supplies can be independently set to 1.5v or 1.8v, depending on the end application. the guard band supplies are independent connection brought out to pins. table 49. power supplies recommended power supply connections ideally, a board should have the power supplies described below: vdd33 and vddio supplies for the fpga logic a single 1.5v source to supply power to fpga and core digital logic. a dedicated 1.5v power supply for the analog power pins. this will allow the end user to minimize noise. the guard band pins can also be sourced from the analog power supplies. tx output buffer power. the power supplies to the tx output buffers should be isolated from the rest of the board power supplies. special care must be taken to minimize noise when providing board level power to these output buffers. the power supply can be 1.5v or 1.8v depending on the end application. rx input buffer power. the power supplies to the rx input buffers should be isolated from the rest of the board power supplies. special care must be taken to minimize noise when providing board level power to these input buffers. the power supply can be 1.5v or 1.8v depending on the end application. recommended power supply filtering scheme the board connections of the various serdes v dd and v ss pins are critical to system performance. an example demonstration board schematic is available at www .latticesemi.com . power supply ?tering is in the form of: a parallel bypass capacitor network consisting of 10 ?, 0.1 ?, and 1.0 ? caps close to the power source. a parallel bypass capacitor network consisting of 0.01 ? and 0.1 ? close to the pin on the orso42g5 and orso82g5. fpga supplies fpga and core digital supply 1.5v analog 1.5v tx output buffers 1.5v/1.8v (v dd ob) rx input buffers 1.5v/1.8v (v dd ib) guard band 1.5v (v dd gb) vdd33 v dd 15 v dd _ana v dd ob_aa v dd ib_aa v dd gb_a vddio0 v dd ob_ab v dd ib_ab v dd gb_b vddio1 v dd ob_ac v dd ib_ac vddio5 v dd ob_ad v dd ib_ad vddio6 v dd ob_ba v dd ib_ba vddio7 v dd ob_bb v dd ib_bb v dd ob_bc v dd ib_bc v dd ob_bd v dd ib_bd
lattice semiconductor orca orso42g5 and orso82g5 data sheet 119 example connections are shown in figure 52. the naming convention for the power supply sources shown in the ?ure are as follows: supply_1.5v tx-rx digital, auxiliary power pins supply_v dd _ana analog power pins supply v dd ib input rx buffer power pins supply_v dd ob output tx buffer power pins figure 52. power supply filtering 0.1 f 10 f v dd 15 supply_1.5 v source pin supply_v dd _ana v dd ib supply_v dd ib v dd ob supply_v dd ob ? network for every 2 pins ? network for every 2 pins ? each for v dd gb_[a,b] ? network for every 2 pins ? network for every 2 pins 1 f 0.01 f 0.1 f 0.1 f 10 f 1 f 0.01 f 0.1 f v dd _ana 0.1 f 10 f 1 f 0.01 f 0.1 f 0.1 f 10 f 1 f 0.01 f 0.1 f
lattice semiconductor orca orso42g5 and orso82g5 data sheet 120 package information package pinouts table 50 provides the number of user-programmable i/os available for each available package. table 50. i/o summary table 51 provides the package pin and pin function for the orso42g5 and orso82g5 fpsc and packages. the bond pad name is identi?d in the pio nomenclature used in the isplever system software design editor. the bank column provides information as to which output voltage level bank the given pin is in. the group column pro- vides information as to the group of pins the given pin is in. this is used to show which vref pin is used to provide the reference voltage for single-ended limited-swing i/os. if none of these buffer types (such as sstl, gtl, hstl) are used in a given group, then the vref pin is available as an i/o pin. when the number of fpga bond pads exceeds the number of package pins, bond pads are unused. when the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). when a package pin is to be left as a no connect for a speci? die, it is indicated as a note in the device column for the fpga. the tables provide no information on unused pads. the differential pairs within each bank are physically arranged so that the ball locations for the pair are adjacent in either the horizontal, vertical or diagonal directions. v ref pins, shown in the pin description columns in table 51 are associated to the bank and group (e.g., vref_tl_01 is the v ref for group one of the top left (tl) bank. device orso42g5 orso82g5 user programmable i/o 204 372 available programmable differential pair pins 166 330 fpga con?uration pins 7 7 fpga dedicated function pins 2 2 core function pins 32 71 vdd15 49 63 vdd33 8 10 vddio 34 32 vss 112 91 vddgb 2 2 vddib 4 8 vddob 8 12 vdd_ana 22 8 core lv_ref pins 1 1 no connect 0 2 total package pins 484 680 table 51. orso42g5 484-pin pbgam pinout bm484 vddio bank vref group i/o pin description additional function bm484 pair e4 - - o prd_data rd_data/tdo - c20 - - vdd15 vdd15 - - d3 - - i preset_n reset_n - f5 - - i prd_cfg_n rd_cfg_n - f4 - - i pprgrm_n prgrm_n - c2 0 (tl) 7 io pl2d pll_ck0c/hppll l1c
lattice semiconductor orca orso42g5 and orso82g5 data sheet 121 c1 0 (tl) 7 io pl2c pll_ck0t/hppll l1t f3 0 (tl) 7 io pl3c vref_0_07 - a1 - - vss vss - - d2 0 (tl) 7 io pl4d d5 l2c d1 0 (tl) 7 io pl4c d6 l2t e7 0 (tl) - vddio0 vddio0 - - e2 0 (tl) 8 io pl5d hdc l3c e1 0 (tl) 8 io pl5c ldc_n l3t g3 0 (tl) 8 io pl5a - - g4 0 (tl) 9 io pl6c d7 - f2 0 (tl) 9 io pl7d vref_0_09 l4c f1 0 (tl) 9 io pl7c a17/ppc_a31 l4t g2 0 (tl) 9 io pl8d cs0_n l5c g1 0 (tl) 9 io pl8c cs1 l5t e8 0 (tl) - vddio0 vddio0 - - a2 - - vss vss - - h1 0 (tl) 10 io pl10d init_n l6c h2 0 (tl) 10 io pl10c dout l6t e5 - - vdd15 vdd15 - - h4 0 (tl) 10 io pl11d vref_0_10 - h3 0 (tl) 10 io pl11c a16/ppc_a30 - j1 7 (cl) 1 io pl12d a15/ppc_a29 l7c j2 7 (cl) 1 io pl12c a14/ppc_a28 l7t j4 7 (cl) 1 io pl13c d4 - g7 - - vss vss - - j3 7 (cl) 2 io pl14d rdy/busy_n/rclk - k6 7 (cl) - vddio7 vddio7 - - k1 7 (cl) 2 io pl15d a13/ppc_a27 l8c k2 7 (cl) 2 io pl15c a12/ppc_a26 l8t k3 7 (cl) 3 io pl16c - - k4 7 (cl) 3 io pl17d a11/ppc_a25 - g8 - - vss vss - - f8 - - vdd15 vdd15 - - k5 7 (cl) 4 io pl19d rd_n/mpi_strb_n - l1 7 (cl) 4 io pl20d plck0c l9c l2 7 (cl) 4 io pl20c plck0t l9t l6 7 (cl) - vddio7 vddio7 - - f9 - - vdd15 vdd15 - - g9 - - vss vss - - l3 7 (cl) 5 io pl21d a10/ppc_a24 l10c l4 7 (cl) 5 io pl21c a9/ppc_a23 l10t l5 7 (cl) 5 io pl22d a8/ppc_a22 - f10 - - vdd15 vdd15 - - g10 - - vss vss - - table 51. orso42g5 484-pin pbgam pinout (continued) bm484 vddio bank vref group i/o pin description additional function bm484 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 122 m3 7 (cl) 6 io pl24d plck1c l11c m4 7 (cl) 6 io pl24c plck1t l11t n4 7 (cl) 6 io pl25c a7/ppc_a21 - m2 7 (cl) 6 io pl26d a6/ppc_a20 l12c m1 7 (cl) 6 io pl26c a5/ppc_a19 l12t n3 7 (cl) 7 io pl27d wr_n/mpi_rw - f11 - - vdd15 vdd15 - - n5 7 (cl) 8 io pl28d a4/ppc_a18 - m5 7 (cl) - vddio7 vddio7 - - n2 7 (cl) 8 io pl29d a3/ppc_a17 l13c n1 7 (cl) 8 io pl29c a2/ppc_a16 l13t g11 - - vss vss - - p2 7 (cl) 8 io pl30d a1/ppc_a15 l14c p1 7 (cl) 8 io pl30c a0/ppc_a14 l14t f12 - - vdd15 vdd15 - - p3 7 (cl) 8 io pl31d dp0 l15c p4 7 (cl) 8 io pl31c dp1 l15t r4 6 (bl) 1 io pl32d d8 l16c r3 6 (bl) 1 io pl32c vref_6_01 l16t r2 6 (bl) 1 io pl33d d9 l17c r1 6 (bl) 1 io pl33c d10 l17t g12 - - vss vss - - t3 6 (bl) 2 io pl34d - - p5 6 (bl) - vddio6 vddio6 - - t2 6 (bl) 2 io pl34b - l18c t1 6 (bl) 2 io pl34a - l18t u1 6 (bl) 3 io pl35b d11 l19c u2 6 (bl) 3 io pl35a d12 l19t r5 6 (bl) - vddio6 vddio6 - - v1 6 (bl) 3 io pl36b vref_6_03 l20c v2 6 (bl) 3 io pl36a d13 l20t g13 - - vss vss - - w2 6 (bl) 4 io pl37b - l21c w1 6 (bl) 4 io pl37a vref_6_04 l21t y1 6 (bl) 4 io pl39d pll_ck7c/hppll l22c y2 6 (bl) 4 io pl39c pll_ck7t/hppll l22t u3 - - i ptemp ptemp - f13 - - vdd15 vdd15 - - v4 - - io lvds_r lvds_r - v3 - - vdd33 vdd33 - - f17 - - vdd15 vdd15 - - w3 6 (bl) 5 io pb2a dp2 - aa2 6 (bl) 5 io pb2c pll_ck6t/ppll l23t ab2 6 (bl) 5 io pb2d pll_ck6c/ppll l23c table 51. orso42g5 484-pin pbgam pinout (continued) bm484 vddio bank vref group i/o pin description additional function bm484 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 123 aa3 6 (bl) 5 io pb4a vref_6_05 l24t ab3 6 (bl) 5 io pb4b dp3 l24c t5 6 (bl) - vddio6 vddio6 - - h7 - - vss vss - - y4 6 (bl) 6 io pb5c vref_6_06 l25t w4 6 (bl) 6 io pb5d d14 l25c t8 6 (bl) - vddio6 vddio6 - - aa4 6 (bl) 7 io pb6c d15 l26t ab4 6 (bl) 7 io pb6d d16 l26c h8 - - vss vss - - w5 6 (bl) 7 io pb7c d17 l27t y5 6 (bl) 7 io pb7d d18 l27c t9 6 (bl) - vddio6 vddio6 - - aa5 6 (bl) 7 io pb8c vref_6_07 l28t ab5 6 (bl) 7 io pb8d d19 l28c h9 - - vss vss - - v6 6 (bl) 8 io pb9c d20 - g6 - - vdd15 vdd15 - - w6 6 (bl) 8 io pb10c vref_6_08 l29t y6 6 (bl) 8 io pb10d d22 l29c h10 - - vss vss - - aa6 6 (bl) 9 io pb11c d23 l30t ab6 6 (bl) 9 io pb11d d24 l30c u6 6 (bl) - vddio6 vddio6 - - w7 6 (bl) 9 io pb12c vref_6_09 l31t y7 6 (bl) 9 io pb12d d25 l31c h11 - - vss vss - - v7 6 (bl) 10 io pb14a - - u7 6 (bl) - vddio6 vddio6 - - aa7 6 (bl) 10 io pb14c vref_6_10 l32t ab7 6 (bl) 10 io pb14d d28 l32c v8 6 (bl) 11 io pb15a - - h12 - - vss vss - - w8 6 (bl) 11 io pb15c d29 l33t y8 6 (bl) 11 io pb15d d30 l33c u8 6 (bl) 11 io pb16a - - aa8 6 (bl) 11 io pb16c vref_6_11 l34t ab8 6 (bl) 11 io pb16d d31 l34c v9 5 (bc) 1 io pb17a - - w9 5 (bc) 1 io pb17c - l35t y9 5 (bc) 1 io pb17d - l35c u9 5 (bc) 1 io pb18a - - aa9 5 (bc) 1 io pb18c vref_5_01 l36t ab9 5 (bc) 1 io pb18d - l36c table 51. orso42g5 484-pin pbgam pinout (continued) bm484 vddio bank vref group i/o pin description additional function bm484 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 124 g16 - - vdd15 vdd15 - - h13 - - vss vss - - ab10 5 (bc) 2 io pb19a - l37t aa10 5 (bc) 2 io pb19b - l37c w10 5 (bc) 2 io pb19c pbck0t l38t y10 5 (bc) 2 io pb19d pbck0c l38c v10 5 (bc) 2 io pb20a - - u13 5 (bc) - vddio5 vddio5 - - ab11 5 (bc) 2 io pb20c vref_5_02 l39t aa11 5 (bc) 2 io pb20d - l39c u10 5 (bc) 2 io pb21a - - h6 - - vdd15 vdd15 - - y11 5 (bc) 3 io pb21c - l40t w11 5 (bc) 3 io pb21d vref_5_03 l40c u11 5 (bc) 3 io pb22a - - j7 - - vss vss - - ab12 5 (bc) 3 io pb22c - l41t aa12 5 (bc) 3 io pb22d - l41c u12 5 (bc) 3 io pb23a - - y12 5 (bc) 3 io pb23c pbck1t l42t w12 5 (bc) 3 io pb23d pbck1c l42c v11 5 (bc) 3 io pb24a - - j8 - - vss vss - - ab13 5 (bc) 4 io pb24c - l43t aa13 5 (bc) 4 io pb24d - l43c v12 5 (bc) 4 io pb25a - - u14 5 (bc) - vddio5 vddio5 - - ab14 5 (bc) 4 io pb25c - l44t aa14 5 (bc) 4 io pb25d vref_5_04 l44c j9 - - vss vss - - y13 5 (bc) 5 io pb26c - l45t w13 5 (bc) 5 io pb26d vref_5_05 l45c u15 5 (bc) - vddio5 vddio5 - - ab15 5 (bc) 5 io pb27c - l46t aa15 5 (bc) 5 io pb27d - l46c ab16 5 (bc) 6 io pb28c - l47t aa16 5 (bc) 6 io pb28d vref_5_06 l47c h14 - - vdd15 vdd15 - - y14 5 (bc) 6 io pb29c - l48t w14 5 (bc) 6 io pb29d - l48c j10 - - vss vss - - ab17 5 (bc) 7 io pb30c - l49t aa17 5 (bc) 7 io pb30d - l49c u16 5 (bc) - vddio5 vddio5 - - table 51. orso42g5 484-pin pbgam pinout (continued) bm484 vddio bank vref group i/o pin description additional function bm484 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 125 y15 5 (bc) 7 io pb31c vref_5_07 l50t w15 5 (bc) 7 io pb31d - l50c v13 5 (bc) - vddio5 vddio5 - - ab18 5 (bc) 8 io pb33c - l51t aa18 5 (bc) 8 io pb33d vref_5_08 l51c j11 - - vss vss - - v14 5 (bc) 8 io pb34d - - v16 5 (bc) 9 io pb35b - - y16 5 (bc) 9 io pb36c - l52t w16 5 (bc) 9 io pb36d - l52c v15 - - vdd33 vdd33 - - j12 - - vss vss - - h15 - - vdd15 vdd15 - - j13 - - vss vss - - j6 - - vdd15 vdd15 - - j14 - - vss vss - - y17 - - vdd33 vdd33 - - k8 - - vss vss - - j15 - - vdd15 vdd15 - - k7 - - vdd15 vdd15 - - y18 - - vdd33 vdd33 - - k9 - - vss vss - - w21 - - vss vss - - w22 - - vddgb_b vddgb_b - - f18 - - vdd_ana vdd_ana - - v21 - - o rext_b - - v22 - - o rextn_b - - u21 - - i refclkn_b - hsn_1 u22 - - i refclkp_b - hsp_1 e20 - - vss vss - - g17 - - vdd_ana vdd_ana - - g18 - - vdd_ana vdd_ana - - j16 - - vdd_ana vdd_ana - - j17 - - vdd_ana vdd_ana - - t20 - - vddib vddib_bc - - j18 - - vdd_ana vdd_ana - - t21 - - i hdinn_bc - hsn_2 f19 - - vss vss - - t22 - - i hdinp_bc - hsp_2 j19 - - vdd_ana vdd_ana - - f20 - - vss vss - - k16 - - vdd_ana vdd_ana - - r20 - - vddob vddob_bc - - r21 - - o hdoutn_bc - hsn_3 table 51. orso42g5 484-pin pbgam pinout (continued) bm484 vddio bank vref group i/o pin description additional function bm484 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 126 g19 - - vss vss - - r22 - - o hdoutp_bc - hsp_3 p21 - - vddob vddob_bc - - h16 - - vss vss - - p22 - - vddib vddib_bd - - k17 - - vdd_ana vdd_ana - - n22 - - i hdinn_bd - hsn_4 h17 - - vss vss - - n21 - - i hdinp_bd - hsp_4 k18 - - vdd_ana vdd_ana - - h18 - - vss vss - - k19 - - vdd_ana vdd_ana - - p20 - - vddob vddob_bd - - m22 - - o hdoutn_bd - hsn_5 h19 - - vss vss - - m21 - - o hdoutp_bd - hsp_5 n20 - - vddob vddob_bd - - l16 - - vss vss - - l17 - - vss vss - - m20 - - vddob vddob_ad - - l22 - - o hdoutp_ad - hsp_6 l18 - - vss vss - - l21 - - o hdoutn_ad - hsn_6 l20 - - vddob vddob_ad - - n16 - - vdd_ana vdd_ana - - l19 - - vss vss - - n17 - - vdd_ana vdd_ana - - k22 - - i hdinp_ad - hsp_7 m16 - - vss vss - - k21 - - i hdinn_ad - hsn_7 n18 - - vdd_ana vdd_ana - - k20 - - vddib vddib_ad - - m17 - - vss vss - - j20 - - vddob vddob_ac - - j21 - - o hdoutp_ac - hsp_8 m18 - - vss vss - - j22 - - o hdoutn_ac - hsn_8 h20 - - vddob vddob_ac - - n19 - - vdd_ana vdd_ana - - m19 - - vss vss - - p16 - - vdd_ana vdd_ana - - h21 - - i hdinp_ac - hsp_9 r16 - - vss vss - - h22 - - i hdinn_ac - hsn_9 table 51. orso42g5 484-pin pbgam pinout (continued) bm484 vddio bank vref group i/o pin description additional function bm484 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 127 p17 - - vdd_ana vdd_ana - - g20 - - vddib vddib_ac - - p18 - - vdd_ana vdd_ana - - p19 - - vdd_ana vdd_ana - - t17 - - vdd_ana vdd_ana - - t18 - - vdd_ana vdd_ana - - r17 - - vss vss - - g21 - - i refclkp_a - hsp_10 g22 - - i refclkn_a - hsn_10 f21 - - o rextn_a - - f22 - - o rext_a - - u18 - - vdd_ana vdd_ana - - e21 - - vddgb_a vddgb_a - - e22 - - vss vss - - d21 - - o psys_rssig_all - - d22 - - i psys_dobistn - - d20 - - vdd33 vdd33 - - k15 - - vdd15 vdd15 - - k10 - - vss vss - - l7 - - vdd15 vdd15 - - d19 - - i pbist_test_enn - - d18 - - i ploop_test_enn - - l15 - - vdd15 vdd15 - - e17 - - i pasb_pdn - - k11 - - vss vss - - d17 - - vdd33 vdd33 - - m7 - - vdd15 vdd15 - - c21 - - i pasb_resetn - - c22 - - i pasb_tristn - - k12 - - vss vss - - e16 - - i pasb_testclk - - m15 - - vdd15 vdd15 - - c17 - - vdd33 vdd33 - - d16 1 (tc) 7 io pt36d - - c16 1 (tc) 7 io pt36b - - f14 1 (tc) 7 io pt35d - - f15 1 (tc) 7 io pt35b - - e14 1 (tc) 7 io pt34d vref_1_07 - e15 1 (tc) 8 io pt34b - - d15 1 (tc) 8 io pt33d - l53c c15 1 (tc) 8 io pt33c vref_1_08 l53t e12 1 (tc) - vddio1 vddio1 - - c18 1 (tc) 8 io pt32d - l54c c19 1 (tc) 8 io pt32c - l54t table 51. orso42g5 484-pin pbgam pinout (continued) bm484 vddio bank vref group i/o pin description additional function bm484 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 128 k13 - - vss vss - - b21 1 (tc) 9 io pt31d - l55c a21 1 (tc) 9 io pt31c vref_1_09 l55t e13 1 (tc) - vddio1 vddio1 - - d14 1 (tc) 9 io pt30d - l56c c14 1 (tc) 9 io pt30c - l56t k14 - - vss vss - - b20 1 (tc) 9 io pt29d - l57c a20 1 (tc) 9 io pt29c - l57t n7 - - vdd15 vdd15 - - b19 1 (tc) 1 io pt28d - l58c a19 1 (tc) 1 io pt28c - l58t l8 - - vss vss - - d13 1 (tc) 1 io pt27d vref_1_01 l59c c13 1 (tc) 1 io pt27c - l59t e18 1 (tc) - vddio1 vddio1 - - a18 1 (tc) 1 io pt27b - l60c b18 1 (tc) 1 io pt27a - l60t a17 1 (tc) 2 io pt26d - l61c b17 1 (tc) 2 io pt26c vref_1_02 l61t l9 - - vss vss - - d12 1 (tc) 2 io pt25d - l62c c12 1 (tc) 2 io pt25c - l62t e19 1 (tc) - vddio1 vddio1 - - a16 1 (tc) 3 io pt24d - l63c b16 1 (tc) 3 io pt24c vref_1_03 l63t a15 1 (tc) 3 io pt23d - l64c b15 1 (tc) 3 io pt23c - l64t f16 1 (tc) - vddio1 vddio1 - - e11 1 (tc) 3 io pt22d - - l10 - - vss vss - - d11 1 (tc) 4 io pt21d - l65c c11 1 (tc) 4 io pt21c - l65t a14 1 (tc) 4 io pt20d - l66c b14 1 (tc) 4 io pt20c - l66t a13 1 (tc) 4 io pt19d - l67c b13 1 (tc) 4 io pt19c vref_1_04 l67t g14 1 (tc) - vddio1 vddio1 - - l11 - - vss vss - - n15 - - vdd15 vdd15 - - d10 1 (tc) 5 io pt18d ptck1c l68c c10 1 (tc) 5 io pt18c ptck1t l68t a12 1 (tc) 5 io pt17d ptck0c l69c b12 1 (tc) 5 io pt17c ptck0t l69t table 51. orso42g5 484-pin pbgam pinout (continued) bm484 vddio bank vref group i/o pin description additional function bm484 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 129 p6 - - vdd15 vdd15 - - a11 1 (tc) 5 io pt16d vref_1_05 l70c b11 1 (tc) 5 io pt16c - l70t l12 - - vss vss - - d9 1 (tc) 6 io pt15d - l71c c9 1 (tc) 6 io pt15c - l71t g15 1 (tc) - vddio1 vddio1 - - b10 1 (tc) 6 io pt14d - l72c a10 1 (tc) 6 io pt14c vref_1_06 l72t b9 0 (tl) 1 io pt13d mpi_rtry_n l73c a9 0 (tl) 1 io pt13c mpi_ack_n l73t d8 0 (tl) 1 io pt12d m0 l74c c8 0 (tl) 1 io pt12c m1 l74t a22 - - vss vss - - b8 0 (tl) 2 io pt12b mpi_clk l75c a8 0 (tl) 2 io pt12a a21/mpi_burst_n l75t c7 0 (tl) 2 io pt11d m2 l76c d7 0 (tl) 2 io pt11c m3 l76t e9 0 (tl) - vddio0 vddio0 - - e6 0 (tl) 2 io pt11a mpi_tea_n - f6 - - vdd15 vdd15 - - b7 0 (tl) 3 io pt9d vref_0_03 l77c a7 0 (tl) 3 io pt9c - l77t a6 0 (tl) 3 io pt8d d0 l78c b6 0 (tl) 3 io pt8c tms l78t c6 0 (tl) 4 io pt7d a20/mpi_bdip_n l79c d6 0 (tl) 4 io pt7c a19/mpi_tsz1 l79t b1 - - vss vss - - a5 0 (tl) 4 io pt6d a18/mpi_tsz0 l80c b5 0 (tl) 4 io pt6c d3 l80t c5 0 (tl) 5 io pt5d d1 l81c d5 0 (tl) 5 io pt5c d2 l81t b2 - - vss vss - - a4 0 (tl) 5 io pt4d tdi l82c b4 0 (tl) 5 io pt4c tck l82t e10 0 (tl) - vddio0 vddio0 - - b22 - - vss vss - - c4 0 (tl) 6 io pt2d pll_ck1c/ppll l83c d4 0 (tl) 6 io pt2c pll_ck1t/ppll l83t a3 - - o pcfg_mpi_irq cfg_irq_n/mpi_irq_n - b3 - - io pcclk cclk - f7 - - vdd15 vdd15 - - c3 - - io pdone done - e3 - - vdd33 vdd33 - - table 51. orso42g5 484-pin pbgam pinout (continued) bm484 vddio bank vref group i/o pin description additional function bm484 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 130 p15 - - vdd15 vdd15 - - r6 - - vdd15 vdd15 - - r15 - - vdd15 vdd15 - - t4 - - vdd15 vdd15 - - w19 - - vdd15 vdd15 - - y3 - - vdd15 vdd15 - - y19 - - vdd15 vdd15 - - y20 - - vdd15 vdd15 - - t15 - - vdd15 vdd15 - - t16 - - vdd15 vdd15 - - u4 - - vdd15 vdd15 - - t12 - - vdd15 vdd15 - - t13 - - vdd15 vdd15 - - t14 - - vdd15 vdd15 - - t6 - - vdd15 vdd15 - - t7 - - vdd15 vdd15 - - t10 - - vdd15 vdd15 - - t11 - - vdd15 vdd15 - - g5 0 (tl) - vddio0 vddio0 - - h5 0 (tl) - vddio0 vddio0 - - j5 0 (tl) - vddio0 vddio0 - - v17 5 (bc) - vddio5 vddio5 - - w17 5 (bc) - vddio5 vddio5 - - w18 5 (bc) - vddio5 vddio5 - - m6 7 (cl) - vddio7 vddio7 - - n6 7 (cl) - vddio7 vddio7 - - u5 - - vdd15 vdd15 - - u17 - - vdd15 vdd15 - - v5 - - vdd15 vdd15 - - v18 - - vdd15 vdd15 - - r18 - - vss vss - - r19 - - vss vss - - t19 - - vss vss - - u19 - - vss vss - - u20 - - vss vss - - v19 - - vss vss - - v20 - - vss vss - - w20 - - vss vss - - y21 - - vss vss - - y22 - - vss vss - - l13 - - vss vss - - l14 - - vss vss - - m8 - - vss vss - - m9 - - vss vss - - table 51. orso42g5 484-pin pbgam pinout (continued) bm484 vddio bank vref group i/o pin description additional function bm484 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 131 m10 - - vss vss - - m11 - - vss vss - - m12 - - vss vss - - m13 - - vss vss - - m14 - - vss vss - - n8 - - vss vss - - n9 - - vss vss - - n10 - - vss vss - - n11 - - vss vss - - n12 - - vss vss - - n13 - - vss vss - - n14 - - vss vss - - p7 - - vss vss - - p8 - - vss vss - - p9 - - vss vss - - p10 - - vss vss - - p11 - - vss vss - - p12 - - vss vss - - p13 - - vss vss - - p14 - - vss vss - - r7 - - vss vss - - r8 - - vss vss - - r9 - - vss vss - - r10 - - vss vss - - r11 - - vss vss - - r12 - - vss vss - - r13 - - vss vss - - r14 - - vss vss - - aa1 - - vss vss - - aa19 - - vss vss - - aa20 - - vss vss - - aa21 - - vss vss - - aa22 - - vss vss - - ab1 - - vss vss - - ab19 - - vss vss - - ab20 - - vss vss - - ab21 - - vss vss - - ab22 - - vss vss - - table 51. orso42g5 484-pin pbgam pinout (continued) bm484 vddio bank vref group i/o pin description additional function bm484 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 132 table 52. orso82g5 680-pin pbgam (fpbga) pinout bm68 0 v dd io bank vref group i/o pin description additional function bm680 pair ab20 vss vss c3 v dd 33 v dd 33 e4 o prd_data rd_data/tdo f5 i preset_n reset_n g5 i prd_cfg_n rd_cfg_n d3 i pprgrm_n prgrm_n a2 0 (tl) v dd io0 v dd io0 f4 0 (tl) 7 io pl2d pll_ck0c/hppll l21c_a0 g4 0 (tl) 7 io pl2c pll_ck0t/hppll l21t_a0 b3 0 (tl) v dd io0 v dd io0 c2 0 (tl) 7 io pl3d l22c_d0 b1 0 (tl) 7 io pl3c vref_0_07 l22t_d0 a1 vss v ss j5 0 (tl) 7 io pl4d d5 l23c_a0 h5 0 (tl) 7 io pl4c d6 l23t_a0 b7 0 (tl) v dd io0 v dd io0 e3 0 (tl) 8 io pl4b l24c_a0 f3 0 (tl) 8 io pl4a vref_0_08 l24t_a0 c1 0 (tl) 8 io pl5d hdc l25c_d0 d2 0 (tl) 8 io pl5c ldc_n l25t_d0 a34 v ss v ss g3 0 (tl) 8 io pl5b l26c_d0 h4 0 (tl) 8 io pl5a l26t_d0 e2 0 (tl) 9 io pl6d testcfg l27c_d0 d1 0 (tl) 9 io pl6c d7 l27t_d0 c5 0 (tl) v dd io0 v dd io0 f2 0 (tl) 9 io pl7d vref_0_09 l28c_d0 e1 0 (tl) 9 io pl7c a17/ppc_a31 l28t_d0 aa13 v ss v ss j4 0 (tl) 9 io pl7b l29c_d0 k5 0 (tl) 9 io pl7a l29t_d0 h3 0 (tl) 9 io pl8d cs0_n l30c_d0 g2 0 (tl) 9 io pl8c cs1 l30t_d0 c9 0 (tl) v dd io0 v dd io0 l5 0 (tl) 9 io pl8b l31c_d0 k4 0 (tl) 9 io pl8a l31t_d0 h2 0 (tl) 10 io pl9d l32c_d0 j3 0 (tl) 10 io pl9c l32t_d0 aa14 v ss v ss m5 0 (tl) 10 io pl9b f1 0 (tl) 10 io pl10d init_n l33c_a0 g1 0 (tl) 10 io pl10c dout l33t_a0 k3 0 (tl) 10 io pl11d vref_0_10 l34c_d0
lattice semiconductor orca orso42g5 and orso82g5 data sheet 133 j2 0 (tl) 10 io pl11c a16/ppc_a30 l34t_d0 aa15 v ss v ss l4 0 (tl) 10 io pl11b n5 7 (cl) 1 io pl12d a15/ppc_a29 l1c_d0 m4 7 (cl) 1 io pl12c a14/ppc_a28 l1t_d0 aa3 7 (cl) v dd io7 v dd io7 l3 7 (cl) 1 io pl12b l2c_d0 k2 7 (cl) 1 io pl12a l2t_d0 h1 7 (cl) 1 io pl13d vref_7_01 l3c_a0 j1 7 (cl) 1 io pl13c d4 l3t_a0 v18 v ss v ss n4 7 (cl) 2 io pl13b l4c_d0 p5 7 (cl) 2 io pl13a l4t_d0 m3 7 (cl) 2 io pl14d rdy/busy_n/rclk l5c_d0 l2 7 (cl) 2 io pl14c vref_7_02 l5t_d0 ac2 7 (cl) v dd io7 v dd io7 k1 7 (cl) 2 io pl14b l6c_a0 l1 7 (cl) 2 io pl14a l6t_a0 p4 7 (cl) 2 io pl15d a13/ppc_a27 l7c_a0 p3 7 (cl) 2 io pl15c a12/ppc_a26 l7t_a0 v19 v ss v ss m2 7 (cl) 2 io pl15b l8c_a0 m1 7 (cl) 2 io pl15a l8t_a0 n2 7 (cl) 3 io pl16d l9c_a0 n1 7 (cl) 3 io pl16c l9t_a0 n3 7 (cl) v dd io7 v dd io7 r4 7 (cl) 3 io pl16b p2 7 (cl) 3 io pl17d a11/ppc_a25 l10c_d0 r3 7 (cl) 3 io pl17c vref_7_03 l10t_d0 w16 v ss v ss r5 7 (cl) 3 io pl17b p1 7 (cl) 3 io pl18d l11c_a0 r1 7 (cl) 3 io pl18c l11t_a0 t5 7 (cl) 3 io pl18b l12c_a0 t4 7 (cl) 3 io pl18a l12t_a0 t3 7 (cl) 4 io pl19d rd_n/mpi_strb_n l13c_a0 t2 7 (cl) 4 io pl19c vref_7_04 l13t_a0 w17 v ss v ss u1 7 (cl) 4 io pl19b l14c_a0 t1 7 (cl) 4 io pl19a l14t_a0 u4 7 (cl) 4 io pl20d plck0c l15c_a0 u5 7 (cl) 4 io pl20c plck0t l15t_a0 r2 7 (cl) v dd io7 v dd io7 table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 134 u2 7 (cl) 4 io pl20b l16c_d0 v1 7 (cl) 4 io pl20a l16t_d0 w18 v ss v ss v2 7 (cl) 5 io pl21d a10/ppc_a24 l17c_a0 v3 7 (cl) 5 io pl21c a9/ppc_a23 l17t_a0 w19 v ss v ss v4 7 (cl) 5 io pl21b l18c_a0 v5 7 (cl) 5 io pl21a l18t_a0 w4 7 (cl) 5 io pl22d a8/ppc_a22 l19c_a0 w3 7 (cl) 5 io pl22c vref_7_05 l19t_a0 w1 7 (cl) 5 io pl22b l20c_a0 y1 7 (cl) 5 io pl22a l20t_a0 y2 7 (cl) 5 io pl23d l21c_d0 aa1 7 (cl) 5 io pl23c l21t_d0 y13 v ss v ss y4 7 (cl) 5 io pl23b l22c_a0 y3 7 (cl) 5 io pl23a l22t_a0 y5 7 (cl) 6 io pl24d plck1c l23c_a0 w5 7 (cl) 6 io pl24c plck1t l23t_a0 u3 7 (cl) v dd io7 v dd io7 ab1 7 (cl) 6 io pl24b l24c_d0 aa2 7 (cl) 6 io pl24a l24t_d0 ab2 7 (cl) 6 io pl25d vref_7_06 l25c_d0 ac1 7 (cl) 6 io pl25c a7/ppc_a21 l25t_d0 y14 v ss v ss aa4 7 (cl) 6 io pl25b ab4 7 (cl) 6 io pl26d a6/ppc_a20 l26c_a0 ab3 7 (cl) 6 io pl26c a5/ppc_a19 l26t_a0 w2 7 (cl) v dd io7 v dd io7 ad1 7 (cl) 7 io pl26b ae1 7 (cl) 7 io pl27d wr_n/mpi_rw l27c_d0 ad2 7 (cl) 7 io pl27c vref_7_07 l27t_d0 ac3 7 (cl) 7 io pl27b l28c_a0 ac4 7 (cl) 7 io pl27a l28t_a0 af1 7 (cl) 8 io pl28d a4/ppc_a18 l29c_d0 ae2 7 (cl) 8 io pl28c vref_7_08 l29t_d0 ab5 7 (cl) 8 io pl29d a3/ppc_a17 l30c_a0 aa5 7 (cl) 8 io pl29c a2/ppc_a16 l30t_a0 y15 v ss v ss ad3 7 (cl) 8 io pl29b ag1 7 (cl) 8 io pl30d a1/ppc_a15 l31c_d0 af2 7 (cl) 8 io pl30c a0/ppc_a14 l31t_d0 ad4 7 (cl) 8 io pl30b l32c_d0 table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 135 ae3 7 (cl) 8 io pl30a l32t_d0 ad5 7 (cl) 8 io pl31d dp0 l33c_a0 ac5 7 (cl) 8 io pl31c dp1 l33t_a0 y20 v ss v ss ag2 7 (cl) 8 io pl31b l34c_d0 ah1 7 (cl) 8 io pl31a l34t_d0 af3 6 (bl) 1 io pl32d d8 l1c_a0 ag3 6 (bl) 1 io pl32c vref_6_01 l1t_a0 al7 6 (bl) v dd io6 v dd io6 ae4 6 (bl) 1 io pl32b l2c_a0 af4 6 (bl) 1 io pl32a l2t_a0 ae5 6 (bl) 1 io pl33d d9 l3c_a0 af5 6 (bl) 1 io pl33c d10 l3t_a0 r21 v ss v ss aj1 6 (bl) 2 io pl34d l4c_d0 ah2 6 (bl) 2 io pl34c vref_6_02 l4t_d0 am5 6 (bl) v dd io6 v dd io6 ak1 6 (bl) 2 io pl34b l5c_d0 aj2 6 (bl) 2 io pl34a l5t_d0 r22 v ss v ss ag4 6 (bl) 3 io pl35b d11 l6c_d0 ah3 6 (bl) 3 io pl35a d12 l6t_d0 al1 6 (bl) 3 io pl36d l7c_d0 ak2 6 (bl) 3 io pl36c l7t_d0 am9 6 (bl) v dd io6 v dd io6 am1 6 (bl) 3 io pl36b vref_6_03 l8c_d0 al2 6 (bl) 3 io pl36a d13 l8t_d0 aj3 6 (bl) 4 io pl37d t16 v ss v ss aj4 6 (bl) 4 io pl37b l9c_a0 ah4 6 (bl) 4 io pl37a vref_6_04 l9t_a0 ak3 6 (bl) 4 io pl38c an2 6 (bl) v dd io6 v dd io6 ag5 6 (bl) 4 io pl38b l10c_a0 ah5 6 (bl) 4 io pl38a l10t_a0 an1 6 (bl) 4 io pl39d pll_ck7c/hppll l11c_d0 am2 6 (bl) 4 io pl39c pll_ck7t/hppll l11t_d0 t17 v ss v ss al3 6 (bl) 4 io pl39b l12c_d0 ak4 6 (bl) 4 io pl39a l12t_d0 t18 v ss v ss am3 i ptemp ptemp an3 6 (bl) v dd io6 v dd io6 table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 136 aj5 io lvds_r lvds_r al4 v dd 33 v dd 33 t19 v ss v ss ak5 v dd 33 v dd 33 am4 6 (bl) 5 io pb2a dp2 l13t_d0 al5 6 (bl) 5 io pb2b l13c_d0 an7 6 (bl) v dd io6 v dd io6 ap3 6 (bl) 5 io pb2c pll_ck6t/ppll l14t_a0 ap4 6 (bl) 5 io pb2d pll_ck6c/ppll l14c_a0 an4 6 (bl) 5 io pb3b u16 v ss v ss ak6 6 (bl) 5 io pb3c l15t_a0 ak7 6 (bl) 5 io pb3d l15c_a0 al6 6 (bl) 5 io pb4a vref_6_05 l16t_a0 am6 6 (bl) 5 io pb4b dp3 l16c_a0 ap1 6 (bl) v dd io6 v dd io6 an5 6 (bl) 6 io pb4c l17t_a0 ap5 6 (bl) 6 io pb4d l17c_a0 ak8 6 (bl) 6 io pb5b u17 v ss v ss ap6 6 (bl) 6 io pb5c vref_6_06 l18t_d0 ap7 6 (bl) 6 io pb5d d14 l18c_d0 am7 6 (bl) 6 io pb6a l19t_d0 an6 6 (bl) 6 io pb6b l19c_d0 ap2 6 (bl) v dd io6 v dd io6 al8 6 (bl) 7 io pb6c d15 l20t_a0 al9 6 (bl) 7 io pb6d d16 l20c_a0 ak9 6 (bl) 7 io pb7b u18 v ss v ss an8 6 (bl) 7 io pb7c d17 l21t_a0 am8 6 (bl) 7 io pb7d d18 l21c_a0 an9 6 (bl) 7 io pb8a l22t_d0 ap8 6 (bl) 7 io pb8b l22c_d0 ak10 6 (bl) 7 io pb8c vref_6_07 l23t_a0 al10 6 (bl) 7 io pb8d d19 l23c_a0 ap9 6 (bl) 8 io pb9b u19 v ss v ss am10 6 (bl) 8 io pb9c d20 l24t_a0 am11 6 (bl) 8 io pb9d d21 l24c_a0 ak11 6 (bl) 8 io pb10b an10 6 (bl) 8 io pb10c vref_6_08 l25t_a0 ap10 6 (bl) 8 io pb10d d22 l25c_a0 an11 6 (bl) 9 io pb11a l26t_a0 table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 137 ap11 6 (bl) 9 io pb11b l26c_a0 v16 v ss v ss al12 6 (bl) 9 io pb11c d23 l27t_a0 ak12 6 (bl) 9 io pb11d d24 l27c_a0 an12 6 (bl) 9 io pb12a l28t_a0 am12 6 (bl) 9 io pb12b l28c_a0 ap12 6 (bl) 9 io pb12c vref_6_09 l29t_a0 ap13 6 (bl) 9 io pb12d d25 l29c_a0 am13 6 (bl) 9 io pb13a l30t_d0 an14 6 (bl) 9 io pb13b l30c_d0 v17 v ss v ss ap14 6 (bl) 10 io pb13c d26 l31t_a0 ap15 6 (bl) 10 io pb13d d27 l31c_a0 ak13 6 (bl) 10 io pb14a l32t_a0 ak14 6 (bl) 10 io pb14b l32c_a0 am14 6 (bl) 10 io pb14c vref_6_10 l33t_a0 al14 6 (bl) 10 io pb14d d28 l33c_a0 ap17 6 (bl) 11 io pb15a l34t_a0 ap16 6 (bl) 11 io pb15b l34c_a0 am15 6 (bl) 11 io pb15c d29 l35t_d0 an16 6 (bl) 11 io pb15d d30 l35c_d0 am17 6 (bl) 11 io pb16a l36t_a0 am16 6 (bl) 11 io pb16b l36c_a0 ap18 6 (bl) 11 io pb16c vref_6_11 l37t_a0 ap19 6 (bl) 11 io pb16d d31 l37c_a0 al16 5 (bc) 1 io pb17a l1t_d0 ak15 5 (bc) 1 io pb17b l1c_d0 n22 v ss v ss an18 5 (bc) 1 io pb17c l2t_a0 an19 5 (bc) 1 io pb17d l2c_a0 ap20 5 (bc) 1 io pb18a l3t_a0 ap21 5 (bc) 1 io pb18b l3c_a0 al17 5 (bc) 1 io pb18c vref_5_01 l4t_d0 ak16 5 (bc) 1 io pb18d l4c_d0 p13 v ss v ss am19 5 (bc) 2 io pb19a l5t_a0 am18 5 (bc) 2 io pb19b l5c_a0 p14 v ss v ss an20 5 (bc) 2 io pb19c pbck0t l6t_a0 am20 5 (bc) 2 io pb19d pbck0c l6c_a0 ak17 5 (bc) 2 io pb20a l7t_d0 al18 5 (bc) 2 io pb20b l7c_d0 al11 5 (bc) v dd io5 v dd io5 table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 138 ap22 5 (bc) 2 io pb20c vref_5_02 l8t_d0 an21 5 (bc) 2 io pb20d l8c_d0 am22 5 (bc) 2 io pb21a l9t_a0 am21 5 (bc) 2 io pb21b l9c_a0 ap23 5 (bc) 3 io pb21c l10t_d0 an22 5 (bc) 3 io pb21d vref_5_03 l10c_d0 al19 5 (bc) 3 io pb22a l11t_d0 ak18 5 (bc) 3 io pb22b l11c_d0 p15 v ss v ss ap24 5 (bc) 3 io pb22c l12t_d0 an23 5 (bc) 3 io pb22d l12c_d0 ap25 5 (bc) 3 io pb23a l13t_a0 ap26 5 (bc) 3 io pb23b l13c_a0 al13 5 (bc) v dd io5 v dd io5 al20 5 (bc) 3 io pb23c pbck1t l14t_d0 ak19 5 (bc) 3 io pb23d pbck1c l14c_d0 ak20 5 (bc) 3 io pb24a l15t_d0 al21 5 (bc) 3 io pb24b l15c_d0 p20 v ss v ss an24 5 (bc) 4 io pb24c l16t_d0 am23 5 (bc) 4 io pb24d l16c_d0 an26 5 (bc) 4 io pb25a l17t_a0 an25 5 (bc) 4 io pb25b l17c_a0 al15 5 (bc) v dd io5 v dd io5 ak21 5 (bc) 4 io pb25c l18t_d0 al22 5 (bc) 4 io pb25d vref_5_04 l18c_d0 am24 5 (bc) 4 io pb26a l19t_d0 al23 5 (bc) 4 io pb26b l19c_d0 p21 v ss v ss ap27 5 (bc) 5 io pb26c l20t_a0 an27 5 (bc) 5 io pb26d vref_5_05 l20c_a0 al24 5 (bc) 5 io pb27a l21t_d0 am25 5 (bc) 5 io pb27b l21c_d0 an13 5 (bc) v dd io5 v dd io5 ap28 5 (bc) 5 io pb27c l22t_a0 ap29 5 (bc) 5 io pb27d l22c_a0 an29 5 (bc) 6 io pb28b p22 v ss v ss am27 5 (bc) 6 io pb28c l23t_d0 an28 5 (bc) 6 io pb28d vref_5_06 l23c_d0 am26 5 (bc) 6 io pb29b ak22 5 (bc) 6 io pb29c l24t_a0 ak23 5 (bc) 6 io pb29d l24c_a0 table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 139 al25 5 (bc) 7 io pb30b r13 v ss v ss ap30 5 (bc) 7 io pb30c l25t_a0 ap31 5 (bc) 7 io pb30d l25c_a0 ak24 5 (bc) 7 io pb31b an15 5 (bc) v dd io5 v dd io5 am29 5 (bc) 7 io pb31c vref_5_07 l26t_a0 am28 5 (bc) 7 io pb31d l26c_a0 an30 5 (bc) 7 io pb32b r14 v ss v ss ak25 5 (bc) 7 io pb32c l27t_d0 al26 5 (bc) 7 io pb32d l27c_d0 an17 5 (bc) v dd io5 v dd io5 al27 5 (bc) 8 io pb33c l28t_a0 al28 5 (bc) 8 io pb33d vref_5_08 l28c_a0 an31 5 (bc) 8 io pb34b r15 v ss v ss ak26 5 (bc) 8 io pb34d am30 5 (bc) 9 io pb35b al29 5 (bc) 9 io pb35d vref_5_09 ak27 5 (bc) 9 io pb36b r20 v ss v ss al30 5 (bc) 9 io pb36c l29t_d0 ak29 5 (bc) 9 io pb36d l29c_d0 ak28 v dd 33 v dd 33 aa16 v dd 15 v dd 15 ap32 io pschar_ldio9 ap33 io pschar_ldio8 an32 io pschar_ldio7 am31 io pschar_ldio6 aa17 v dd 15 v dd 15 am32 v dd 33 v dd 33 al31 io pschar_ldio5 am33 io pschar_ldio4 aa18 v dd 15 v dd 15 ak30 io pschar_ldio3 al32 io pschar_ldio2 aa19 v dd 15 v dd 15 ab16 v dd 15 v dd 15 ak31 v dd 33 v dd 33 aj30 io pschar_ldio1 ak33 io pschar_ldio0 ak34 io pschar_ckio1 table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 140 aj31 io pschar_ckio0 aj33 io pschar_xck aj34 io pschar_wdsync ah30 io pschar_cv ah31 io pschar_bytsync ah32 o atmout_b (no connect) ah33 v ss v ss ah34 v dd gb_b v dd gb_b aa32 vdd_ana vdd_ana af30 rext_b af31 rextn_b ae30 i refclkn_b ae31 i refclkp_b ab32 v ss v ss ad30 v dd ib v dd ib_ba ad32 vdd_ana vdd_ana af33 i hdinn_ba ac32 v ss v ss af34 i hdinp_ba ae32 vdd_ana vdd_ana ad31 v ss v ss k32 vdd_ana vdd_ana ae33 o hdoutn_ba af32 v ss v ss ae34 o hdoutp_ba ac30 v dd ob v dd ob_ba ag30 v ss v ss ab30 v dd ib v dd ib_bb ad33 i hdinn_bb ag31 v ss v ss ad34 i hdinp_bb ac31 v ss v ss ac33 o hdoutn_bb ag32 v ss v ss ac34 o hdoutp_bb ab31 v dd ob v dd ob_bb ag33 v ss v ss aa30 v dd ib v dd ib_bc ab33 i hdinn_bc ag34 v ss v ss ab34 i hdinp_bc aa31 v ss v ss y30 v dd ob v dd ob_bc table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 141 aa33 o hdoutn_bc h30 v ss v ss aa34 o hdoutp_bc y31 v dd ob v dd ob_bc h31 v ss v ss w30 v dd ib v dd ib_bd y33 i hdinn_bd h32 v ss v ss y34 i hdinp_bd w31 v ss v ss v30 v dd ob v dd ob_bd w33 o hdoutn_bd h33 v ss v ss w34 o hdoutp_bd v31 v dd ob v dd ob_bd h34 v ss v ss j32 v ss v ss u31 v dd ob v dd ob_ad t34 o hdoutp_ad m32 v ss v ss t33 o hdoutn_ad u30 v dd ob v dd ob_ad t31 v ss v ss r34 i hdinp_ad n32 v ss v ss r33 i hdinn_ad t30 v dd ib v dd ib_ad u32 v ss v ss r31 v dd ob v dd ob_ac p34 o hdoutp_ac u33 v ss v ss p33 o hdoutn_ac r30 v dd ob v dd ob_ac p31 v ss v ss n34 i hdinp_ac u34 v ss v ss n33 i hdinn_ac p30 v dd ib v dd ib_ac v32 v ss v ss m34 o hdoutp_ab v33 v ss v ss m33 o hdoutn_ab n31 v dd ob v dd ob_ab table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 142 m31 v ss v ss l34 i hdinp_ab v34 v ss v ss l33 i hdinn_ab n30 v dd ib v dd ib_ab k34 o hdoutp_aa k33 o hdoutn_aa m30 v dd ob v dd ob_aa l32 vdd_ana vdd_ana l31 v ss v ss p32 vdd_ana vdd_ana j34 i hdinp_aa j33 i hdinn_aa r32 vdd_ana vdd_ana l30 v dd ib v dd ib_aa k31 refclkp_a k30 refclkn_a j31 o rextn_a j30 o rext_a y32 vdd_ana vdd_ana g34 v dd gb_a v dd gb_a g33 v ss v ss g32 o atmout_a (no connect) g31 i preserve01 f33 i preserve02 g30 i preserve03 f31 o psys_rssig_all f30 i psys_dobistn e31 v dd 33 v dd 33 ab17 v dd 15 v dd 15 ab18 v dd 15 v dd 15 d32 i pbist_test_enn e30 i ploop_test_enn ab19 v dd 15 v dd 15 d31 i pasb_pdn c32 i pmp_testclk c31 v dd 33 v dd 33 aj32 v dd 15 v dd 15 b32 i pasb_resetn a33 i pasb_tristn b31 i pmp_testclk_enn a32 i pasb_testclk ak32 v dd 15 v dd 15 table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 143 ab21 v ss v ss a31 v dd 33 v dd 33 b30 1 (tc) 7 io pt36d ab22 v ss v ss c30 1 (tc) 7 io pt36b d30 1 (tc) 7 io pt35d b13 1 (tc) v dd io1 v dd io1 e29 1 (tc) 7 io pt35b e28 1 (tc) 7 io pt34d vref_1_07 an33 v ss vss d29 1 (tc) 8 io pt34b b29 1 (tc) 8 io pt33d l1c_a0 c29 1 (tc) 8 io pt33c vref_1_08 l1t_a0 b15 1 (tc) v dd io1 v dd io1 e27 1 (tc) 8 io pt32d l2c_a0 e26 1 (tc) 8 io pt32c l2t_a0 ap34 vss vss a30 1 (tc) 8 io pt32b a29 1 (tc) 9 io pt31d l3c_d3 e25 1 (tc) 9 io pt31c vref_1_09 l3t_d3 b17 1 (tc) v dd io1 v dd io1 e24 1 (tc) 9 io pt31a b28 1 (tc) 9 io pt30d l4c_a0 c28 1 (tc) 9 io pt30c l4t_a0 b2 vss vss d28 1 (tc) 9 io pt30a c27 1 (tc) 9 io pt29d l5c_a0 d27 1 (tc) 9 io pt29c l5t_a0 e23 1 (tc) 9 io pt29b l6c_a0 e22 1 (tc) 9 io pt29a l6t_a0 d26 1 (tc) 1 io pt28d l7c_a0 d25 1 (tc) 1 io pt28c l7t_a0 b33 vss vss d24 1 (tc) 1 io pt28b l8c_a0 d23 1 (tc) 1 io pt28a l8t_a0 c26 1 (tc) 1 io pt27d vref_1_01 l9c_a0 c25 1 (tc) 1 io pt27c l9t_a0 d11 1 (tc) v dd io1 v dd io1 e21 1 (tc) 1 io pt27b l10c_a0 e20 1 (tc) 1 io pt27a l10t_a0 d22 1 (tc) 2 io pt26d l11c_a0 d21 1 (tc) 2 io pt26c vref_1_02 l11t_a0 e34 vss vss table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 144 a28 1 (tc) 2 io pt26b b26 1 (tc) 2 io pt25d l12c_a0 b25 1 (tc) 2 io pt25c l12t_a0 d13 1 (tc) v dd io1 v dd io1 b27 1 (tc) 2 io pt25b a27 1 (tc) 3 io pt24d l13c_a0 a26 1 (tc) 3 io pt24c vref_1_03 l13t_a0 n13 vss vss c24 1 (tc) 3 io pt24b c22 1 (tc) 3 io pt23d l14c_a0 c23 1 (tc) 3 io pt23c l14t_a0 d15 1 (tc) v dd io1 v dd io1 b24 1 (tc) 3 io pt23b d20 1 (tc) 3 io pt22d l15c_a0 d19 1 (tc) 3 io pt22c l15t_a0 n14 vss vss e19 1 (tc) 3 io pt22b l16c_a0 e18 1 (tc) 3 io pt22a l16t_a0 c21 1 (tc) 4 io pt21d l17c_a0 c20 1 (tc) 4 io pt21c l17t_a0 a25 1 (tc) 4 io pt21b l18c_a0 a24 1 (tc) 4 io pt21a l18t_a0 b23 1 (tc) 4 io pt20d l19c_a0 a23 1 (tc) 4 io pt20c l19t_a0 n15 vss vss e17 1 (tc) 4 io pt20b l20c_a0 e16 1 (tc) 4 io pt20a l20t_a0 b22 1 (tc) 4 io pt19d l21c_a0 b21 1 (tc) 4 io pt19c vref_1_04 l21t_a0 c18 1 (tc) 4 io pt19b l22c_a0 c19 1 (tc) 4 io pt19a l22t_a0 n20 vss vss a22 1 (tc) 5 io pt18d ptck1c l23c_a0 a21 1 (tc) 5 io pt18c ptck1t l23t_a0 n21 vss vss d17 1 (tc) 5 io pt18b l24c_a0 d18 1 (tc) 5 io pt18a l24t_a0 b20 1 (tc) 5 io pt17d ptck0c l25c_a0 b19 1 (tc) 5 io pt17c ptck0t l25t_a0 a20 1 (tc) 5 io pt17b l26c_a0 a19 1 (tc) 5 io pt17a l26t_a0 a18 1 (tc) 5 io pt16d vref_1_05 l27c_a0 b18 1 (tc) 5 io pt16c l27t_a0 table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 145 y21 vss vss c17 1 (tc) 5 io pt16b l28c_d0 d16 1 (tc) 5 io pt16a l28t_d0 a17 1 (tc) 6 io pt15d l29c_d0 b16 1 (tc) 6 io pt15c l29t_d0 e15 1 (tc) 6 io pt15b l30c_a0 e14 1 (tc) 6 io pt15a l30t_a0 a16 1 (tc) 6 io pt14d l31c_a0 a15 1 (tc) 6 io pt14c vref_1_06 l31t_a0 y22 vss vss d14 1 (tc) 6 io pt14b c16 0 (tl) 1 io pt13d mpi_rtry_n l1c_a0 c15 0 (tl) 1 io pt13c mpi_ack_n l1t_a0 d7 0 (tl) v dd io0 v dd io0 c14 0 (tl) 1 io pt13b l2c_a0 b14 0 (tl) 1 io pt13a vref_0_01 l2t_a0 a14 0 (tl) 1 io pt12d m0 l3c_a0 a13 0 (tl) 1 io pt12c m1 l3t_a0 aa20 vss vss e12 0 (tl) 2 io pt12b mpi_clk l4c_a0 e13 0 (tl) 2 io pt12a a21/mpi_burst_n l4t_a0 c13 0 (tl) 2 io pt11d m2 l5c_a0 c12 0 (tl) 2 io pt11c m3 l5t_a0 b12 0 (tl) 2 io pt11b vref_0_02 l6c_a0 a12 0 (tl) 2 io pt11a mpi_tea_n l6t_a0 d12 0 (tl) 3 io pt10d l7c_d0 c11 0 (tl) 3 io pt10c l7t_d0 b11 0 (tl) 3 io pt10b a11 0 (tl) 3 io pt9d vref_0_03 l8c_a0 a10 0 (tl) 3 io pt9c l8t_a0 aa21 vss vss b10 0 (tl) 3 io pt9b e11 0 (tl) 3 io pt8d d0 l9c_d0 d10 0 (tl) 3 io pt8c tms l9t_d0 c10 0 (tl) 3 io pt8b a9 0 (tl) 4 io pt7d a20/mpi_bdip_n l10c_a0 b9 0 (tl) 4 io pt7c a19/mpi_tsz1 l10t_a0 aa22 vss vss e10 0 (tl) 4 io pt7b a8 0 (tl) 4 io pt6d a18/mpi_tsz0 l11c_a0 b8 0 (tl) 4 io pt6c d3 l11t_a0 d9 0 (tl) 4 io pt6b vref_0_04 l12c_d0 c8 0 (tl) 4 io pt6a l12t_d0 table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 146 e9 0 (tl) 5 io pt5d d1 l13c_d0 d8 0 (tl) 5 io pt5c d2 l13t_d0 ab13 vss vss a7 0 (tl) 5 io pt5b l14c_a0 a6 0 (tl) 5 io pt5a vref_0_05 l14t_a0 c7 0 (tl) 5 io pt4d tdi l15c_d0 b6 0 (tl) 5 io pt4c tck l15t_d0 e8 0 (tl) 5 io pt4b l16c_a0 e7 0 (tl) 5 io pt4a l16t_a0 a5 0 (tl) 6 io pt3d l17c_a0 b5 0 (tl) 6 io pt3c vref_0_06 l17t_a0 ab14 vss vss c6 0 (tl) 6 io pt3b l18c_a0 d6 0 (tl) 6 io pt3a l18t_a0 c4 0 (tl) 6 io pt2d pll_ck1c/ppll l19c_a0 b4 0 (tl) 6 io pt2c pll_ck1t/ppll l19t_a0 a4 0 (tl) 6 io pt2b l20c_a0 a3 0 (tl) 6 io pt2a l20t_a0 d5 o pcfg_mpi_irq cfg_irq_n/mpi_irq_n e6 io pcclk cclk d4 io pdone done e5 v dd 33 v dd 33 ab15 vss vss al33 v dd 15 v dd 15 al34 v dd 15 v dd 15 am34 v dd 15 v dd 15 an34 v dd 15 v dd 15 b34 v dd 15 v dd 15 c33 v dd 15 v dd 15 c34 v dd 15 v dd 15 d33 v dd 15 v dd 15 d34 v dd 15 v dd 15 e32 v dd 15 v dd 15 e33 v dd 15 v dd 15 f32 v dd 15 v dd 15 f34 v dd 15 v dd 15 n16 v dd 15 v dd 15 n17 v dd 15 v dd 15 n18 v dd 15 v dd 15 n19 v dd 15 v dd 15 p16 v dd 15 v dd 15 p17 v dd 15 v dd 15 p18 v dd 15 v dd 15 table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 147 p19 v dd 15 v dd 15 r16 v dd 15 v dd 15 r17 v dd 15 v dd 15 r18 v dd 15 v dd 15 r19 v dd 15 v dd 15 t13 v dd 15 v dd 15 t14 v dd 15 v dd 15 t15 v dd 15 v dd 15 t20 v dd 15 v dd 15 t21 v dd 15 v dd 15 t22 v dd 15 v dd 15 u13 v dd 15 v dd 15 u14 v dd 15 v dd 15 u15 v dd 15 v dd 15 u20 v dd 15 v dd 15 u21 v dd 15 v dd 15 u22 v dd 15 v dd 15 v13 v dd 15 v dd 15 v14 v dd 15 v dd 15 v15 v dd 15 v dd 15 v20 v dd 15 v dd 15 v21 v dd 15 v dd 15 v22 v dd 15 v dd 15 w13 v dd 15 v dd 15 w14 v dd 15 v dd 15 w15 v dd 15 v dd 15 w20 v dd 15 v dd 15 w21 v dd 15 v dd 15 w22 v dd 15 v dd 15 y16 v dd 15 v dd 15 y17 v dd 15 v dd 15 y18 v dd 15 v dd 15 y19 v dd 15 v dd 15 t32 nc nc w32 nc nc table 52. orso82g5 680-pin pbgam (fpbga) pinout (continued) bm68 0v dd io bank vref group i/o pin description additional function bm680 pair
lattice semiconductor orca orso42g5 and orso82g5 data sheet 148 package thermal characteristics summary there are three thermal parameters that are in common use: ja , jc, and jc. it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system air?w. ja this is the thermal resistance from junction to ambient (theta-ja): (1) where t j is the junction temperature, t a, is the ambient air temperature, and q is the chip power. experimentally, ja is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced con- vection measurements. a controlled amount of power (q) is dissipated in the test chips heater resistor, the chips temperature (t j ) is determined by the forward drop on the diodes, and the ambient temperature (t a ) is noted. note that ja is expressed in units of ?/w. jc this jedec designated parameter correlates the junction temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance and it is de?ed by: (2) where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. dur- ing the ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. jc is also expressed in units of ?/w. jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is de?ed by: (3) the parameters in this equation have been de?ed above. however, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates jc from jc. jc is a true thermal resistance and is expressed in units of ?/w. jb this is the thermal resistance from junction to board. it is de?ed by: (4) where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other parameters on the right-hand side have been de?ed above. this is considered a true thermal resistance, and the measure- ment is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. ja = t j ?t a q = t j ?t c q jc = t j ?t c q jb = t j ?t b q
lattice semiconductor orca orso42g5 and orso82g5 data sheet 149 note that jb is expressed in units of ?/w and that this parameter and the way it is measured are still being dis- cussed by the jedec committee. fpsc maximum junction temperature once the power dissipated by the fpsc has been determined, the maximum junction temperature of the fpsc can be found. this is needed to determine if speed derating of the device from the 85 ? junction temperature used in all of the delay tables is needed. derating calculations for other temperatures than 85 ? and for other voltages can be made within the isplever software environment. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in ?), the maximum junction temperature is approximated by: (5) package thermal characteristics the thermal characteristics of the 484-ball pbgam (fpbga with heat spreader) used for the ort42g5, 680-ball pbgam (fpbga with heat spreader) and 680-ball fpbga used for the ort82g5 are available in the thermal man- agement section of the lattice web site at www .latticesemi.com . heat sink vendors for bga packages the estimated worst-case power requirements for the orso42g5 and orso82g5 are in the 3 w to 5 w range. consequently, for most applications an external heat sink will be required. table 53 lists, in alphabetical order, heat sink vendors who advertise heat sinks aimed at the bga market. table 53. heat sink vendors package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 54 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capacitance of the lead to the near- est neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. resistance values are in m . the parasitic values in table 54 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designers model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. vendor location phone aavid thermal technology laconia, nh (603) 527-2152 chip coolers warwick, ri (800) 227-0254 ierc burbank, ca (818) 842-7277 r-theta buffalo, ny (800) 388-5428 sanyo denki torrance, ca (310) 783-5400 thermalloy dallas, tx (214) 243-4321 wake?ld engineering wake?ld, ma (617) 246-0874 t jmax = t amax + (q ? jb )
lattice semiconductor orca orso42g5 and orso82g5 data sheet 150 table 54. orca typical package parasitics figure 53. package parasitics package outline drawings package outline drawings for the 484-ball pbgam (fpbga) used for the orso42g5 and 680-ball pbgam (fpbga) used for the orso82g5 are available at the package diagrams section of the lattice semiconductor web site at www .latticesemi.com . l sw l mw r w c 1 c 2 c m l sl l ml 3.8 1.3 250 1.0 1.0 0.3 2.8-5 0.5 -1 pad n board pads c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 pad n + 1 l sw r w l sl circuit pad n+1 pad n package pads
lattice semiconductor orca orso42g5 and orso82g5 data sheet 151 part number description device type options ordering information conventional packaging commercial 1 industrial 1 device voltage orso42g5 1.5v internal 3.3/2.5/1.8/1.5v i/o orso82g5 1.5v internal 3.3/2.5/1.8/1.5v i/o device family part number speed grade package type ball count grade orso42g5 ORSO42G5-3BM484C 3 pbgam (fpbga with heat spreader) 484 c orso42g5-2bm484c 2 pbgam (fpbga with heat spreader) 484 c orso42g5-1bm484c 1 pbgam (fpbga with heat spreader) 484 c orso82g5 orso82g5-3bm680c 3 pbgam (fpbga with heat spreader) 680 c orso82g5-2bm680c 2 pbgam (fpbga with heat spreader) 680 c orso82g5-1bm680c 1 pbgam (fpbga with heat spreader) 680 c 1. for all but the slowest commercial speed grade, the speed grades on these devices are dual marked. for example, the commercia l speed grade -2xxxxxc is also marked with the industrial grade -1xxxxxi. the commercial grade is always one speed grade faster than th e associated dual mark industrial grade. the slowest commercial speed grade is marked as commercial grade only. device family part number speed grade package type ball count grade orso42g5 orso42g5-2bm484i 2 pbgam (fpbga with heat spreader) 484 i orso42g5-1bm484i 1 pbgam (fpbga with heat spreader) 484 i orso82g5 orso82g5-2bm680i 2 pbgam (fpbga with heat spreader) 680 i orso82g5-1bm680i 1 pbgam (fpbga with heat spreader) 680 i 1. for all but the slowest commercial speed grade, the speed grades on these devices are dual marked. for example, the commercia l speed grade -2xxxxxc is also marked with the industrial grade -1xxxxxi. the commercial grade is always one speed grade faster than th e associated dual mark industrial grade. the slowest commercial speed grade is marked as commercial grade only. device family orso42g5 = 4 serdes channels orso82g5 = 8 serdes channels orsox2g5 ?x x xxx xxx speed grade package bm = fine-pitch plastic ball grid array pbgam (fpbga with heat spreader) bmn = lead-free fine-pitch plastic ball grid array pbgam (fpbga with heat spreader) fn = lead-free fine-pitch plastic ball grid array (fpbga with no heat spreader) grade c = commercial i = industrial ball count 484 680
lattice semiconductor orca orso42g5 and orso82g5 data sheet 152 lead-free packaging commercial 1 industrial 1 device family part number speed grade package type ball count grade orso42g5 orso42g5-3bmn484c 3 lead-free pbgam (fpbga with heat spreader) 484 c orso42g5-2bmn484c 2 lead-free pbgam (fpbga with heat spreader) 484 c orso42g5-1bmn484c 1 lead-free pbgam (fpbga with heat spreader) 484 c orso82g5 orso82g5-3fn680c 3 lead-free fpga (no heat spreader) 2 680 c orso82g5-2fn680c 2 lead-free fpga (no heat spreader) 2 680 c orso82g5-1fn680c 1 lead-free fpga (no heat spreader) 2 680 c 1. for all the slowest commercial speed grade, the speed grades on these devices are dual marked. for example, the commercial s peed grade -2xxxxxc is also marked with the industrial grade -1xxxxxi. the commercial grade is always one speed grade faster than th e associated dual mark industrial grade. the slowest commercial speed grade is marked as commercial grade only. 2. refer to the thermal management document at www .latticesemi.com for ja and jc information. device family part number speed grade package type ball count grade orso42g5 orso42g5-2bmn484i 2 lead-free pbgam (fpbga with heat spreader) 484 i orso42g5-1bmn484i 1 lead-free pbgam (fpbga with heat spreader) 484 i orso82g5 orso82g5-2fn680i 2 lead-free fpga (no heat spreader) 2 680 i orso82g5-1fn680i 1 lead-free fpga (no heat spreader) 2 680 i 1. for all the slowest commercial speed grade, the speed grades on these devices are dual marked. for example, the commercial s peed grade -2xxxxxc is also marked with the industrial grade -1xxxxxi. the commercial grade is always one speed grade faster than th e associated dual mark industrial grade. the slowest commercial speed grade is marked as commercial grade only. 2. refer to the thermal management document at www .latticesemi.com for ja and jc information.

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